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參數資料
| 型號： | IDT70825L20PFB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY (SARAM⑩) |
| 中文描述： | 高速8K的× 16順序訪問隨機存取存儲器（單存取RAM⑩） |
| 文件頁數： | 5/21頁 |
| 文件大小： | 319K |
| 代理商： | IDT70825L20PFB |
IDT70825S/L
HIGH-SPEED 8K x 16 SEQUENTIAL ACCESS RANDOM ACCESS MEMORY
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.31
5
3016 tbl 08
DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE
AND SUPPLY VOLTAGE RANGE
(1)
(VCC = 5.0V
±
10%)
70825X20
Com'l. Only
70825X25
Com'l. Only
Typ.
(2)
Max. Typ.
(2)
Max. Typ.
(2)
Max. Unit
—
—
160
—
—
160
170
360
160
170
310
160
—
—
20
—
—
20
25
70
20
25
50
20
—
—
95
—
—
95
105
250
95
105
220
95
—
—
1.0
—
—
0.2
1.0
15
1.0
0.2
5
0.2
—
—
90
—
—
90
70825X35
70825X45
Test
Symbol
I
CC
Parameter
Dynamic Operating
Current
(Both Ports Active)
Condition
CE
= V
IL
, Outputs
Open,
SCE
= V
IL
(5)
f = f
MAX
(3)
SCE
and
CE
>
V
IH
(7)
Version Typ.
(2)
Max.
MIL.
S
L
COM’L. S
L
MIL.
S
L
COM’L. S
L
MIL.
S
L
COM’L. S
L
MIL.
S
L
COM’L. S
L
MIL.
S
L
—
—
180
180
—
—
25
25
—
—
—
380
330
—
—
70
50
—
——
260
230
—
—
15
5
—
—
400
340
340
290
85
65
70
50
290
250
240
210
30
10
15
5
260
215
155
155
155
155
16
16
16
16
90
90
90
90
1.0
0.2
1.0
0.2
85
85
400
340
340
290
85
65
70
50
290
250
240
210
30
10
15
5
260
215
mA
I
SB
1
Standby Current
(Both Ports - TTL Level
CMD
= V
IH
Inputs)
mA
f = f
MAX
(3)
CE
or
SCE
=
V
IH
Active Port Outputs
Open, f = f
MAX
(3)
I
SB
2
Standby Current
(One Port - TTL Level
Input)
mA
115
115
—
—
1.0
0.2
—
—
I
SB
3
Full Standby Current
(Both Ports - CMOS
Level Inputs)
Both Ports
CE
and
SCE
≥
V
CC
- 0.2V
(6,7)
V
IN
≥
V
CC
- 0.2V or
V
IN
≤
0.2V, f = 0
(4)
One Port
CE
or
SCE
≥
V
CC
- 0.2V
(6)
Outputs Open
(Active port), f
= f
MAX
(3)
COM’L. S
V
IN
≥
V
CC
- 0.2V or
V
IN
≤
0.2V
mA
I
SB
4
Full Standby Current
(One Port - CMOS
Level Inputs)
mA
110
240
100
230
90
220
85
220
L
110
200
100
190
90
180
85
180
NOTES:
1. "X" in part number indicates power rating (S or L).
2. V
CC
= 5V, Ta = +25
°
C; guaranteed by device characterization but not production tested.
3. At f = f
MAX
, address, control lines (except Output Enable), and SCLK are cycling at the maximum frequency read cycle of 1/tRC.
4. f = 0 means no address or control lines change.
5.
SCE
may transition, but is Low (
SCE
=V
IL
) when clocked in by SCLK.
6.
SCE
may be
≤
0.2V, after it is clocked in, since SCLK=V
IH
must be clocked in prior to powerdown.
7. If one port is enabled (either
CE
or
SCE
= Low) then the other port is disabled (
SCE
or
CE
= High, respectively). CMOS High > Vcc - 0.2V and
Low < 0.2V, and TTL High = V
IH
and Low = V
IL
.
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES
(L VERSION ONLY)
(V
LC
< 0.2V, V
HC
> V
CC
- 0.2V)
Symbol
Parameter
V
DR
V
CC
for Data Retention
I
CCDR
Data Retention Current
Test Condition
V
CC
= 2V
CE
= V
HC
V
IN
= V
HC
or = V
LC
SCE
= V
HC
(4)
when SCLK=
CMD
= V
HC
Min.
2.0
—
—
Typ.
(1)
—
100
100
—
—
Max.
—
4000
1500
—
—
Unit
V
μ
A
MIL.
COM’L.
t
CDR
(3)
t
R
(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
0
ns
ns
t
RC
(2)
NOTES :
1. T
A
= +25
°
C, V
CC
= 2V; guaranteed by device characterization but not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by device characterization, but is not production tested.
4. To initiate data retention,
SCE
= V
IH
must be clocked in.
3016 tbl 09
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