參數(shù)資料
型號: IDT7014S12PF
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: Low-Power JFET-Input Operational Amplifier 8-SO 0 to 70
中文描述: 4K X 9 DUAL-PORT SRAM, 12 ns, PQFP64
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù): 4/7頁
文件大?。?/td> 72K
代理商: IDT7014S12PF
6.11
4
IDT7014S
HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
7014S12
7014S15
7014S20
7014S25 7014S35
Com'l. Only
Com'l. Only
Mil. Only
Symbol
READ CYCLE
t
RC
t
AA
t
AOE
t
OH
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Read Cycle Time
Address Access Time
Output Enable Access Time
Output Hold from Address Change
Output Low-Z Time
(1, 2)
Output High-Z Time
(1, 2)
12
3
12
8
15
3
15
8
20
3
20
10
25
3
25
12
35
3
35
20
ns
ns
ns
ns
t
LZ
3
3
3
3
3
ns
t
HZ
7
7
9
11
15
ns
NOTES:
1. Transition is measured
±
200mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is determined by device characterization, but is not production tested.
2528 tbl 08
TIMING WAVEFORM OF READ CYCLE NO. 1, EITHER SIDE
(1,2)
TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE
(1, 3)
NOTES:
1. R/
W
= V
IH
for Read Cycles.
2.
OE
= V
IL
.
3. Addresses valid prior to
OE
transition LOW.
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE
ADDRESS
DATA
OUT
PREVIOUS DATA VALID
DATA VALID
t
OH
t
OH
t
AA
t
RC
2528 drw 07
2528 drw 08
DATA
OUT
VALID DATA
t
AOE
OE
t
LZ
t
HZ
相關(guān)PDF資料
PDF描述
IDT7014S15J Low-Power JFET-Input Operational Amplifier 8-SO 0 to 70
IDT7014S15PF HIGH-SPEED 4K x 9 DUAL-PORT STATIC RAM
IDT7014S20J Low-Power JFET-Input Operational Amplifier 8-SOIC 0 to 70
IDT7014S20PF Low-Power JFET-Input Operational Amplifier 8-SOIC 0 to 70
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