參數(shù)資料
型號(hào)： IDT7006S35PFB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： Single Synchronous Buck PWM Controller; Package: SOIC; No of Pins: 8; Container: Tape & Reel
中文描述： 16K X 8 DUAL-PORT SRAM, 35 ns, PQFP64
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64
文件頁(yè)數(shù)： 10/20頁(yè)
文件大?。?/td> 263K
代理商： IDT7006S35PFB
6.07
10
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
CONTROLLED TIMING
(1,5,8)
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
CONTROLLED TIMING
(1,5)
NOTES:
1. R/
W
or
CE
must be High during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a Low
CE
and a Low R/
W
for memory array writing cycle.
3. t
WR
is measured from the earlier of
CE
or R/
W
(or
SEM
or R/
W
) going High to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE
or
SEM
Low transition occurs simultaneously with or after the R/
W
Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE
or R/
W
.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured by +/- 500mV from steady state with the
Output Test Load (Figure 2)
8. If
OE
is Low during R/
W
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data
to be placed on the bus for the required t
DW
. If
OE
is High during an R/
W
controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified t
WP
.
9. To access RAM,
CE
= V
IL and
SEM
= V
IH.
To access semaphore
CE
= V
IH
and
SEM
= V
IL.
t
EW
must be met for either condition.
2739 drw 10
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
(3)
(2)
(6)
(9)
CE
or
SEM
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
ADDRESS
DATA
IN
CE
or
SEM
(6)
(4)
(4)
(3)
2739 drw 09
(7)
(7)
(9)
OE
相關(guān)PDF資料
PDF描述
IDT7006S55G Single Synchronous Buck PWM Controller
IDT7006S55GB Single Synchronous Buck PWM Controller; Package: SOIC; No of Pins: 8; Container: Rail
IDT7006S55J Single Synchronous Buck PWM Controller
IDT7006S55PF Single Synchronous Buck PWM Controller; Package: SOIC; No of Pins: 8; Container: Tape & Reel
IDT7006S55PFB Single Synchronous Buck PWM Controller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT7006S35XL 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM
IDT7006S35XLB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM
IDT7006S45F 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM
IDT7006S45FB 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM
IDT7006S45G 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM
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