參數(shù)資料
型號: IDT7006L35PFB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: DRAM
英文描述: HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
中文描述: 16K X 8 DUAL-PORT SRAM, 35 ns, PQFP64
封裝: 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù): 8/20頁
文件大小: 263K
代理商: IDT7006L35PFB
6.07
8
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING OF POWER-UP POWER-DOWN
WAVEFORM OF READ CYCLES
(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE
or
CE
.
2. Timing depends on which signal is de-asserted first,
CE
or
OE
.
3. t
BDD
delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last t
AOE
, t
ACE
, t
AA
or t
BDD
.
5.
SEM
= V
IH
.
CE
2739 drw 08
t
PU
I
CC
I
SB
t
PD
50%
50%
t
RC
R/
W
CE
ADDRESS
t
AA
t
ACE(4)
OE
2739 drw 07
(4)
t
AOE(4)
(1)
t
LZ
t
OH
(2)
t
HZ
(3, 4)
t
BDD
DATA
OUT
BUSY
OUT
VALID DATA
(4)
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