參數(shù)資料
型號(hào)： IDT7006L35PFB
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： DRAM
英文描述： HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
中文描述： 16K X 8 DUAL-PORT SRAM, 35 ns, PQFP64
封裝： 14 X 14 MM, 1.40 MM HEIGHT, TQFP-64
文件頁數(shù)： 6/20頁
文件大?。?/td> 263K
代理商： IDT7006L35PFB
6.07
6
IDT7006S/L
HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE
(1)
(Cont'd.)
(V
CC
= 5.0V
±
10%)
7006X35
7006X55
7006X70
Mil Only
Test
Symbol
I
CC
Parameter
Condition
Version
MIL.
Typ.
(2)
150
140
150
140
13
10
13
10
85
75
85
75
1.0
0.2
1.0
0.2
Max.
300
250
250
210
80
65
60
50
190
160
155
130
30
10
15
5
Typ.
(2)
150
140
150
140
13
10
13
10
85
75
85
75
1.0
0.2
1.0
0.2
Max. Typ.
(2)
Max. Unit
300
140
250
130
250
—
210
—
80
10
65
8
60
—
50
—
190
80
160
70
155
—
130
—
30
1.0
10
0.2
15
—
5
—
Dynamic Operating
Current
(Both Ports Active)
CE
= V
IL
, Outputs Open
SEM
= V
IH
f = f
MAX(3)
S
L
S
L
S
L
S
L
S
L
S
L
S
L
S
L
300
250
—
—
80
65
—
—
190
160
—
—
30
10
—
—
mA
COM’L.
I
SB1
Standby Current
(Both Ports — TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX(3)
MIL.
mA
COM’L.
I
SB2
Standby Current
(One Port — TTL
Level Inputs)
CE
"A"
=V
IL and
CE
L"B"
=V
IH(5)
MIL.
Active Port Outputs Open,
f = f
MAX(3)
SEM
R
=
SEM
L
= V
IH
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
mA
COM’L.
I
SB3
Full Standby Current
(Both Ports — All
CMOS Level Inputs)
MIL.
mA
COM’L.
SEM
R
=
SEM
L
≥
V
CC
-0.2V
Full Standby Current
(One Port — All
CMOS Level Inputs)
I
SB4
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
≥
V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V
Active Port Outputs Open,
f = f
MAX(3)
MIL.
S
80
175
80
175
75
175
mA
L
S
70
80
150
135
70
80
150
135
65
—
150
—
COM’L.
L
70
110
70
110
—
—
DATA RETENTION CHARACTERISTICS OVER ALL TEMPERATURE RANGES (L Version Only)
(V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
(4)
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
V
DR
I
CCDR
V
CC
for Data Retention
Data Retention Current
V
CC
= 2V
CE
≥
V
HC
V
IN
≥
V
HC
or
≤
V
LC
SEM
≥
V
HC
2.0
—
—
0
t
RC(2)
—
100
100
—
—
—
V
μ
A
MIL.
COM’L.
4000
1500
—
—
t
CDR(3)
t
R(3)
Chip Deselect to Data Retention Time
Operation Recovery Time
ns
ns
NOTES:
1. T
A
= +25
°
C, V
CC
= 2V, and are not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed by characterization, but are not production tested.
4. At Vcc = 2V input leakages are undefined
2739 tbl 11
DATA RETENTION MODE
V
CC
CE
2739 drw 05
4.5V
t
CDR
t
R
V
IH
V
DR
V
IH
4.5V
V
DR
2V
≥
DATA RETENTION WAVEFORM
NOTES:
1. "X" in part numbers indicates power rating (S or L).
2. V
CC
= 5V, T
A
= +25
°
C, and are not production tested. I
CC DC =
120mA (typ)
.
3. At f = f
MAX
,
address and I/O'
S
are cycling at the maximum frequency read cycle of 1/t
RC
, and using “AC Test Conditions” of input levels of GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B"is the opposite from port "A".
2739 tbl 10
相關(guān)PDF資料
PDF描述
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