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參數(shù)資料
| 型號： | IDT7005S70JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 70 ns, PQCC68 |
| 封裝： | 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 4/20頁 |
| 文件大小： | 265K |
| 代理商： | IDT7005S70JB |
6.06
12
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
tWH
Write Hold After
BUSY(5)
25
—
25
—
25
—
ns
BUSY TIMING (M/
SSSSS = VIL)
tWB
BUSY Input to Write(4)
0—
ns
tWH
Write Hold After
BUSY
(5)
25
—
25
—
25
—
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay
(1)
—60—80
—95
ns
tDDD
Write Data Valid to Read Data Delay
(1)
—45—65
—80
ns
BUSY TIMING (M/
SSSSS = VIL)
tWB
BUSY Input to Write(4)
0
—
0
—
0
—
0
—
ns
tWH
Write Hold After
BUSY
(5)
12
—
13
—
15
—
17
—
ns
PORT-TO-PORT DELAY TIMING
tWDD
Write Pulse to Data Delay
(1)
—
30
—
30
—
45
—
50
ns
tDDD
Write Data Valid to Read Data Delay
(1)
—
25
—25—35
—35
ns
IDT7005X15 IDT7005X17
IDT7005X20
IDT7005X25
Com'l. Only
Symbol
Parameter
Min. Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/
SSSSS = VIH)
tBAA
BUSY Access Time from Address Match
—
15
—
17
—
20
—
20
ns
tBDA
BUSY Disable Time from Address Not Matched —
15
—
17
—
20
—
20
ns
tBAC
BUSY Access Time from Chip Enable Low
—
15
—
17
—
20
—
20
ns
tBDC
BUSY Disable Time from Chip Enable High
—
15
—
17
—
17
—
17
ns
tAPS
Arbitration Priority Set-up Time
(2)
5
—
5
—
5
—
5
—
ns
tBDD
BUSY Disable to Valid Data
(3)
—
18
—
18
—
30
—
30
ns
tWH
Write Hold After
BUSY(5)
12
—
13
—
15
—
17
—
ns
IDT7005X35
IDT7005X55
IDT7005X70
Mil. Only
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
BUSY TIMING (M/
SSSSS = VIH)
tBAA
BUSY Access Time from Address Match
—
20
—
45
—
45
ns
tBDA
BUSY Disable Time from Address Not Matched
—
20
—
40
—
40
ns
tBAC
BUSY Access Time from Chip Enable Low
—
20
—
40
—
40
ns
tBDC
BUSY Disable Time from Chip Enable High
—
20
—
35
—
35
ns
tAPS
Arbitration Priority Set-up Time
(2)
5—
ns
tBDD
BUSY Disable to Valid Data(3)
—35—40
—45
ns
NOTES:
2738 tbl 15
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and
BUSY".
2. To ensure that the earlier of the two ports wins.
3. tBDD is a calculated parameter and is the greater of 0, tWDD – tWP (actual), or tDDD – tDW (actual).
4. To ensure that the write cycle is inhibited on port "B" during contention with port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. "X" in part numbers indicates power rating (S or L).
AC ELECTRICAL CHARACTERISTICS OVER THE
OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE(6)
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|---|---|
| IDT7005S70PF | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S70PFB | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7005S70L68B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005S70PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S70PFB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S70XLB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7006 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
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