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參數(shù)資料
| 型號： | IDT7005S70JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 70 ns, PQCC68 |
| 封裝： | 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 19/20頁 |
| 文件大小： | 265K |
| 代理商： | IDT7005S70JB |
6.06
8
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
WAVEFORM OF READ CYCLES(5)
NOTES:
1. Timing depends on which signal is asserted last,
OE or CE.
2. Timing depends on which signal is de-asserted first,
CE or OE.
3. tBDD delay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations
BUSY has no relation to valid output data.
4. Start of valid data depends on which timing becomes effective last tAOE, tACE, tAA or tBDD.
5.
SEM = VIH.
CE
2738 drw 08
tPU
ICC
ISB
tPD
50%
tRC
R/
W
CE
ADDR
tAA
OE
2738 drw 07
(4)
tACE
(4)
tAOE
(4)
(1)
tLZ
tOH
(2)
tHZ
(3, 4)
tBDD
DATAOUT
BUSYOUT
VALID DATA
(4)
TIMING OF POWER-UP POWER-DOWN
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7005S70PF | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S70PFB | HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT71V65703 | 256K x 36, 512K x 18 3.3V Synchronous ZBT SRAMs |
| IDT72V7270 | 3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO |
| IDT72V7290 | 3.3 VOLT HIGH-DENSITY SUPERSYNC II 72-BIT FIFO |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7005S70L68B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7005S70PF | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S70PFB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005S70XLB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x8 Dual-Port SRAM |
| IDT7006 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 16K x 8 DUAL-PORT STATIC RAM |
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