參數(shù)資料
型號: IDT7005L55FB
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: SRAM
英文描述: Single, Ultra Low Cost, RRIO CMOS Amplifier
中文描述: 8K X 8 DUAL-PORT SRAM, 55 ns, QFP68
封裝: 0.970 X 0.970 INCH, 0.080 INCH HEIGHT, QFP-68
文件頁數(shù): 5/20頁
文件大小: 189K
代理商: IDT7005L55FB
6.42
IDT7005S/L
High-Speed 8K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
13
2738 drw 13
tDW
tAPS
(1)
ADDR"A"
tWC
DATAOUT "B"
MATCH
tWP
R/
W"A"
DATAIN "A"
ADDR"B"
tDH
VALID
MATCH
BUSY"B"
tBDA
VALID
tBDD
tDDD
(3)
tWDD
Timing Waveform of Write with Port-to-Port Read with BUSY(2,5)
(M/S = VIH)(4)
NOTES:
1. tWH must be met for both
BUSY input (slave) and output (master).
2.
BUSY is asserted on Port "B", blocking R/W"B", until BUSY"B" goes HIGH
3. tWB is only for the 'Slave' Version..
NOTES:
1. To ensure that the earlier of the two ports wins. tAPS is ignored for for M/S = VIL (slave).
2.
CEL = CER = VIL
3.
OE = VIL for the reading port.
4.
If M/
S = VIL (slave), then BUSY is an input (BUSY"A" =VIH), and BUSY"B" = "don't care", for this example.
5.
All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite port "A".
Timing Waveform of Write with BUSY
2738 drw 14
R/
W"A"
BUSY"B"
tWP
tWB
(3)
R/
W"B"
tWH
(1)
(2)
相關(guān)PDF資料
PDF描述
IDT7005L55G Single, Ultra Low Cost, RRIO CMOS Amplifier; Package: SOT-23; No of Pins: 5; Container: Tape & Reel
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