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參數(shù)資料
| 型號： | IDT7005L25JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Dual 2A High-Speed, Low-Side Gate Driver; Package: MLP; No of Pins: 8; Container: Tape & Reel |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 25 ns, PQCC68 |
| 封裝： | 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 265K |
| 代理商： | IDT7005L25JB |
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
6.06
15
WAVEFORM OF INTERRUPT TIMING(1)
TRUTH TABLES
TRUTH TABLE I — INTERRUPT FLAG(1,4)
Left Port
Right Port
R/
W
WL
CE
CEL
OE
OEL A12L-A0L INT
INT
INTL
R/
W
WR
CE
CER
OE
OER A12R-A0R INT
INT
INTR
Function
L
X
1FFF
XXXXX
L
(2)
Set Right
INTR Flag
X
L
1FFF
H
(3)
Reset Right
INTR Flag
XX
X
L
(3)
L
X
1FFE
X
Set Left
INTL Flag
X
L
1FFE
H
(2)
XXXXX
Reset Left
INTL Flag
NOTES:
2738 tbl 17
1. Assumes
BUSYL = BUSYR = VIH.
2. If
BUSYL = VIL, then no change.
3. If
BUSYR = VIL, then no change.
4.
INTR and INTL must be initialized at power-up.
NOTES:
1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from port “A”.
2. See Interrupt truth table.
3. Timing depends on which enable signal (
CE or R/W) asserted last.
4. Timing depends on which enable signal (
CE or R/W) is de-asserted first.
2738 drw 18
ADDR"B"
INTERRUPT CLEAR ADDRESS
CE"B"
OE"B"
tAS
tRC
(3)
tINR(3)
INT"B"
(2)
2738 drw 17
ADDR"A"
INTERRUPT SET ADDRESS
CE"A"
R/
W"A"
tAS
tWC
tWR
(3)
(4)
tINS (3)
INT"B"
(2)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7005L25PF | Dual 2A High-Speed, Low-Side Gate Driver; Package: SOIC; No of Pins: 8; Container: Tape & Reel |
| IDT7005L25PFB | Dual 2A High-Speed, Low-Side Gate Driver; Package: MLP; No of Pins: 8; Container: Tape & Reel |
| IDT7005L35F | Dual 2A High-Speed, Low-Side Gate Driver; Package: SOIC; No of Pins: 8; Container: Tape & Reel |
| IDT7005L35FB | Dual 2A High-Speed, Low-Side Gate Driver; Package: MLP; No of Pins: 8; Container: Tape & Reel |
| IDT7005L35G | Dual 2A High-Speed, Low-Side Gate Driver; Package: SOIC; No of Pins: 8; Container: Tape & Reel |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7005L25PF | 功能描述:IC SRAM 64KBIT 25NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 雙端口，異步 存儲容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7005L25PF8 | 功能描述:IC SRAM 64KBIT 25NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲器:RAM 存儲器類型:SRAM - 同步 存儲容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7005L25PFB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005L25PFI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 25NS 64TQFP |
| IDT7005L25PFI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 25NS 64TQFP |
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