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參數(shù)資料
| 型號(hào)： | IDT7005L25JB |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | DRAM |
| 英文描述： | Dual 2A High-Speed, Low-Side Gate Driver; Package: MLP; No of Pins: 8; Container: Tape & Reel |
| 中文描述： | 8K X 8 DUAL-PORT SRAM, 25 ns, PQCC68 |
| 封裝： | 0.950 X 0.950 INCH, 0.120 INCH HEIGHT, PLASTIC, LCC-68 |
| 文件頁數(shù)： | 2/20頁 |
| 文件大?。?/td> | 265K |
| 代理商： | IDT7005L25JB |
6.06
10
IDT7005S/L
HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, R/
W
W CONTROLLED TIMING(1,5,8)
NOTES:
1. R/
W or CE must be high during all address transitions.
2. A write occurs during the overlap (tEW or tWP) of a Low
CE and a Low R/W for memory array writing cycle.
3. tWR is measured from the earlier of
CE or R/W (or SEM or R/W) going High to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or SEM Low transition occurs simultaneously with or after the R/W Low transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured +/- 500mv from steady state with the Output
Test Load (Figure 2).
8. If
OE is Low during R/W controlled write cycle, the write pulse width must be the larger of tWP or (tWZ + tDW) to allow the I/O drivers to turn off and data
to be placed on the bus for the required tDW. If
OE is High during an R/W controlled write cycle, this requirement does not apply and the write pulse can
be as short as the specified tWP.
9. To access RAM,
CE = VIH and SEM = VIL. To access semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.
TIMING WAVEFORM OF WRITE CYCLE NO. 2,
CE
CE CONTROLLED TIMING(1,5)
R/
W
tWC
tHZ
tAW
tWR
tAS
tWP
DATAOUT
(2)
tWZ
tDW
tDH
tOW
OE
ADDRESS
DATAIN
CE or SEM
(6)
(4)
(3)
2738 drw 09
(7)
(9)
2738 drw 10
tWC
tAS
tWR
tDW
tDH
ADDRESS
DATAIN
R/
W
tAW
tEW
(3)
(2)
(6)
(9)
CE or SEM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT7005L25PF | Dual 2A High-Speed, Low-Side Gate Driver; Package: SOIC; No of Pins: 8; Container: Tape & Reel |
| IDT7005L25PFB | Dual 2A High-Speed, Low-Side Gate Driver; Package: MLP; No of Pins: 8; Container: Tape & Reel |
| IDT7005L35F | Dual 2A High-Speed, Low-Side Gate Driver; Package: SOIC; No of Pins: 8; Container: Tape & Reel |
| IDT7005L35FB | Dual 2A High-Speed, Low-Side Gate Driver; Package: MLP; No of Pins: 8; Container: Tape & Reel |
| IDT7005L35G | Dual 2A High-Speed, Low-Side Gate Driver; Package: SOIC; No of Pins: 8; Container: Tape & Reel |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT7005L25PF | 功能描述:IC SRAM 64KBIT 25NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:45 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 雙端口，異步 存儲(chǔ)容量:128K（8K x 16） 速度:15ns 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:70V25S15PF |
| IDT7005L25PF8 | 功能描述:IC SRAM 64KBIT 25NS 64TQFP RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SRAM - 同步 存儲(chǔ)容量:9M（256K x 36） 速度:75ns 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x14） 包裝:托盤 其它名稱:71V67703S75PFGI |
| IDT7005L25PFB | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:HIGH-SPEED 8K x 8 DUAL-PORT STATIC RAM |
| IDT7005L25PFI | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 25NS 64TQFP |
| IDT7005L25PFI8 | 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 64KBIT 25NS 64TQFP |
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