參數(shù)資料
型號(hào)： IDT6116LA20TD
廠(chǎng)商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi)： DRAM
英文描述： CMOS STATIC RAM 16K (2K x 8 BIT)
中文描述： 2K X 8 STANDARD SRAM, 19 ns, CDIP24
封裝： 0.300 INCH, CERDIP-24
文件頁(yè)數(shù)： 9/10頁(yè)
文件大?。?/td> 91K
代理商： IDT6116LA20TD
5.1
9
IDT6116SA/LA
CMOS STATIC RAM 16K (2K x 8-BIT)
MILITARY AND COMMERCIAL TEMPERATURE RANGES
TIMING WAVEFORM OF WRITE CYCLE NO. 1, (
WE
CONTROLLED TIMING)
(1, 2, 5, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2, (
CS
CONTROLLED TIMING)
(1, 2, 3, 5, 7)
t
WC
NOTES:
1.
WE
or
CS
must be HIGH during all address transitions.
2. A write occurs during the overlap of a LOW
CS
and a LOW
WE
.
3. tWR is measured from the earlier of
CS
or
WE
going HIGH to the end of the write cycle.
4. During this period, the I/O pins are in the output state and the input signals must not be applied.
5. If the
CS
LOW transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in the high-impedance state.
6. Transition is measured
±
500mV from steady state.
7.
OE
is continuously HIGH. If
OE
is LOW during a
WE
controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WHZ
+ t
DW
) to allow the
I/O drivers to turn off and data to be placed on the bus for the required t
DW
. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not
apply and the write pulse is the specified t
WP
. For a
CS
controlled write cycle,
OE
may be LOW with no degradation to t
CW
.
CS
WE
DATA
IN
t
AW
t
CW
t
WR
(3)
t
DW
t
DH
t
AS
3089 drw 10
DATA VALID
ADDRESS
ADDRESS
DATA
OUT
CS
WE
DATA
IN
t
WC
t
AW
3089 drw 09
t
AS
t
WHZ
(6)
(4)
t
DW
t
DH
(4)
t
OW
t
WR
t
CHZ(6)
t
WP(7)
(6)
PREVIOUS DATA VALID
DATA
VALID
DATA VALID
(3)
相關(guān)PDF資料
PDF描述
IDT6116LA55SO Enhanced-JFET Low-Power Low-Offset Dual Operational Amplifier 8-SOIC 0 to 70
IDT6116LA55TD Enhanced-JFET Low-Power Low-Offset Dual Operational Amplifier 8-SOIC 0 to 70
IDT6116LA55TP Enhanced-JFET Low-Power Low-Offset Dual Operational Amplifier 8-SOIC 0 to 70
IDT6116LA55TPB Enhanced-JFET Low-Power Low-Offset Dual Operational Amplifier 8-PDIP 0 to 70
IDT6116LA55Y Enhanced-JFET Low-Power Low-Offset Dual Operational Amplifier 8-PDIP 0 to 70
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IDT6116LA20TDB 制造商:Integrated Device Technology Inc 功能描述:IC SRAM 16KBIT 20NS 24CERDIP
IDT6116LA20TP 功能描述:IC SRAM 16KBIT 20NS 24DIP RoHS:否 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 產(chǎn)品變化通告:Product Discontinuation 26/Apr/2010 標(biāo)準(zhǔn)包裝:136 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步，DDR II 存儲(chǔ)容量:18M（1M x 18） 速度:200MHz 接口:并聯(lián) 電源電壓:1.7 V ~ 1.9 V 工作溫度:0°C ~ 70°C 封裝/外殼:165-TBGA 供應(yīng)商設(shè)備封裝:165-CABGA（13x15） 包裝:托盤(pán) 其它名稱(chēng):71P71804S200BQ
IDT6116LA20TPB 制造商:IDT 制造商全稱(chēng):Integrated Device Technology 功能描述:CMOS STATIC RAM 16K (2K x 8 BIT)
IDT6116LA20TPG 功能描述:IC SRAM 16KBIT 20NS 24DIP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤(pán)
IDT6116LA20TPGI 功能描述:IC SRAM 16KBIT 20NS 24DIP RoHS:是 類(lèi)別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:72 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類(lèi)型:SRAM - 同步 存儲(chǔ)容量:4.5M（256K x 18） 速度:133MHz 接口:并聯(lián) 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 70°C 封裝/外殼:100-LQFP 供應(yīng)商設(shè)備封裝:100-TQFP（14x20） 包裝:托盤(pán)
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