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參數(shù)資料
| 型號(hào)： | IDT5T995PF |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP44 |
| 封裝： | TQFP-44 |
| 文件頁(yè)數(shù)： | 1/10頁(yè) |
| 文件大?。?/td> | 197K |
| 代理商： | IDT5T995PF |
1
INDUSTRIALTEMPERATURERANGE
IDT5T995/A
2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II
FS
PE
LOCK
PLL
3
sOE
REF
/ N
3
FB
3
Skew
Select
Skew
Select
Skew
Select
Skew
Select
3
1Q0
1Q1
1F1:0
2Q0
2Q1
2F1:0
DS1:0
3Q0
3Q1
3F1:0
4Q0
4Q1
4F1:0
PD
TEST
3
MARCH 2001
2001
Integrated Device Technology, Inc.
DSC - 5850/-
c
IDT5T995/A
PRELIMINARY
INDUSTRIAL TEMPERATURE RANGE
2.5V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK II
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5T995 is a high fanout 2.5V PLL based clock driver intended for
high performance computing and data-communications applications. A key
feature of the programmable skew is the ability of outputs to lead or lag the
REF input signal. The IDT5T995 has eight programmable skew outputs in
four banks of 2. Skew is controlled by 3-level input signals that may be hard-
wired to appropriate high-mid-low levels.
The feedback input allows divide-by-functionality from 1 to 12 through the
use of the DS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
When the
sOE pin is held low, all the outputs are synchronously enabled.
However, if
sOE is held high, all the outputs except 2Q0 and 2Q1 are
synchronously disabled. The LOCK output asserts to indicate when Phase
Lock has been achieved.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF. The IDT5T995 has
LVTTL outputs with 12mA balanced drive outputs.
FEATURES:
REF is 3.3V tolerant
4 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency:
Std: 2MHz to 160MHz
A: 2MHz to 200MHz
Output frequency:
Std: 6MHz to 160MHz
A: 6MHz to 200MHz
3-level inputs for skew and PLL range control
3-level inputs for feedback divide selection
multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4)
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Power-down mode
Lock indicator
Standard and A speed grades
Available in 44-pin TQFP Package
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