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參數(shù)資料
| 型號： | IDT5T9890NLI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC68 |
| 封裝： | PLASTIC, VFQFPN-68 |
| 文件頁數(shù)： | 1/37頁 |
| 文件大小： | 277K |
| 代理商： | IDT5T9890NLI8 |
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INDUSTRIALTEMPERATURERANGE
IDT5T9890
EEPROM PROGRAMMABLE 2.5V PROGRAMMABLE SKEW PLL CLOCK DRIVER
NOVEMBER 2004
2004
Integrated Device Technology, Inc.
DSC - 6504/19
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
2.5 VDD
5 pairs of programmable skew outputs
Low skew: 100ps all outputs at same interface level, 250ps all
outputs at different interface levels
Selectable positive or negative edge synchronization
Tolerant of spread spectrum input clock
Synchronous output enable
Selectable inputs
Input frequency: 4.17MHz to 250MHz
Output frequency: 12.5MHz to 250MHz
Internal non-volatile EEPROM
JTAG or I2C bus serial interface for programming
Hot insertable and over-voltage tolerant inputs
Feedback divide selection with multiply ratios of (1-6, 8, 10, 12)
Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
Selectable HSTL, eHSTL, or 1.8V/2.5V LVTTL output interface for
each output bank
Selectable differential or single-ended inputs and ten single-
ended outputs
PLL bypass for DC testing
External differential feedback, internal loop filter
Low Jitter: <75ps cycle-to-cycle, all outputs at same interface
level: <100ps cycle-to-cycle all outputs at different interface
levels
Power-down mode
Lock indicator
Available in VFQFPN package
IDT5T9890
EEPROM PROGRAMMABLE 2.5V
PROGRAMMABLE SKEW PLL
CLOCK DRIVER
DESCRIPTION:
The IDT5T9890 is a 2.5V PLL clock driver intended for high perfor-
mance computing and data-communications applications. A key feature of
the programmable skew is the ability of outputs to lead or lag the REF input
signal. The IDT5T9890 has ten programmable skew outputs in five banks
of two, plus a dedicated differential feedback. Skew is controlled through
the use of JTAG or I2C programming. The redundant input capability allows
for a smooth change over to a secondary clock source when the primary
clock source is absent.
The clock driver can be configured through the use of JTAG/I2C program-
ming. An internal EEPROM will allow the user to save and restore the
configuration of the device.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of JTAG or I2C programming. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by-functionality of 2 or 4.
The IDT5T9890 features a user-selectable, single-ended or differential
inputtotensingle-endedoutputs. Theclockdriveralsoactsasatranslatorfrom
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs. Each
output bank can be individually configured to be either HSTL, eHSTL, 2.5V
LVTTL, or 1.8V LVTTL, including the feedback bank. Also, each clock input
can be individually configured to accept 2.5V LVTTL, 1.8V LVTTL, or
differential signals. The outputs can be synchronously enabled/disabled.
Furthermore, all the outputs can be synchronized with the positive edge
of the REF clock input or the negative edge of REF.
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