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參數(shù)資料
| 型號： | IDT5T9955BFGI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 5T SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA96 |
| 封裝： | GREEN, FBGA-96 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大小： | 137K |
| 代理商： | IDT5T9955BFGI8 |
1
INDUSTRIALTEMPERATURERANGE
IDT5T9955
2.5V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
DECEMBER 2006
2006
Integrated Device Technology, Inc.
DSC 5976/13
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Ref input is 3.3V tolerant
8 pairs of programmable skew outputs
Low skew: 185ps same pair, 250ps same bank, 350ps both
banks
Selectable positive or negative edge synchronization on each
bank: excellent for DSP applications
Synchronous output enable on each bank
Input frequency: 2MHz to 160MHz
Output frequency: 6MHz to 160MHz
3-level inputs for skew and PLL range control
3-level inputs for feedback divide selection multiply / divide
ratios of (1-6, 8, 10, 12) / (2, 4)
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <100ps cycle-to-cycle
Power-down mode on each bank
Lock indicator on each bank
Available in BGA package
FUNCTIONAL BLOCK DIAGRAM
IDT5T9955
2.5V PROGRAMMABLE
SKEW DUAL PLL CLOCK
DRIVER TURBOCLOCK W
DESCRIPTION:
The IDT5T9955 is a high fanout 2.5V PLL based clock driver intended
for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5T9955 has sixteen programmable skew
outputs in eight banks of 2. The two separate PLLs allow the user to
independently control A and B banks. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate high-mid-low levels.
The feedback input allows divide-by-functionality from 1 to 12 through
the use of the xDS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.
When the xsOE pin is held low, all the xbank outputs are synchronously
enabled. However, if xsOE is held high, all the xbank outputs except x2Q0
and x2Q1 are synchronously disabled. The xLOCK output is high when
the xbank PLL has achieved phase lock.
Furthermore, when xPE is held high, all the outputs are synchronized
with the positive edge of the REF clock input. When xPE is held low, all the
outputs are synchronized with the negative edge of REF. The IDT5T9955
has LVTTL outputs with 12mA balanced drive outputs.
BFS
BPE
BLOCK
PLL
3
BsOE
/N
3
BFB
3
Skew
Select
Skew
Select
Skew
Select
Skew
Select
3
B1Q0
B1Q1
B1F1:0
B2Q0
B2Q1
B2F1:0
BDS1:0
B3Q0
B3Q1
B3F1:0
B4Q0
B4Q1
B4F1:0
BPD
3
AFS
APE
ALOCK
PLL
3
A
sOE
REF
/N
3
AFB
3
Skew
Select
3
A1Q0
A1Q1
A1F1:0
A2Q0
A2Q1
A2F1:0
ADS1:0
A3Q0
A3Q1
A3F1:0
A4Q0
A4Q1
A4F1:0
APD
TEST
3
Skew
Select
Skew
Select
Skew
Select
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