參數(shù)資料
型號: IDT5T9310
廠商: Integrated Device Technology, Inc.
英文描述: 2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
中文描述: 2.5伏的LVDS 1:10時鐘緩沖器TERABUFFER二
文件頁數(shù): 3/12頁
文件大?。?/td> 90K
代理商: IDT5T9310
INDUSTRIAL TEMPERATURE RANGE
IDT5T9310
2.5V LVDS 1:10 CLOCK BUFFER TERABUFFER II
3
Symbol
V
DD
V
I
V
O
T
STG
T
J
Description
Max
Unit
V
V
V
°C
°C
Power Supply Voltage
Input Voltage
Output Voltage
(2)
Storage Temperature
Junction Temperature
–0.5 to +3.6
–0.5 to +3.6
–0.5 to V
DD
+0.5
–65 to +150
150
ABSOLUTE MAX IMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUMRATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximumrating
conditions for extended periods may affect reliability.
2. Not to exceed 3.6V.
Symbol
C
IN
Parameter
Input Capacitance
Mn
Typ.
Max.
3
Unit
pF
CAPACITANCE
(1)
(T
A
= +25°C, F = 1.0MHz)
NOTE:
1. This parameter is measured at characterization but not tested
Symbol
T
A
V
DD
Description
Ambient Operating Temperature
Internal Power Supply Voltage
Min.
–40
2.3
Typ.
+25
2.5
Max.
+85
2.7
Unit
°C
V
RECOMMENDED OPERATING RANGE
PIN DESCRIPTION
Symbol
I/O
A
[1:2]
I
A
[1:2]
I
Type
Description
Clock input. A
[1:2]
is the "true" side of the differential clock input.
Complementary clock inputs.
A
[
1:2]
is the complementary side of A
[1:2].
For LVTTL single-ended operation,
A
[
1:2]
should be set to the
desired toggle voltage for A
[1:2]
:
3.3V LVTTL V
REF
= 1650mV
2.5V LVTTL V
REF
= 1250mV
Gate control for differential outputs Q
1
and
Q
1
through Q
5
and
Q
5
. When
G
1
is LOW, the differential outputs are active. When
G
1
is
HIGH, the differential outputs are asynchronously driven to the level designated by GL
(2)
.
Gate control for differential outputs Q
6
and
Q
6
through Q
10
and
Q
10
. When
G
2
is LOW, the differential outputs are active. When
G
2
is
HIGH, the differential outputs are asynchronously driven to the level designated by GL
(2)
.
Specifies output disable level. If HIGH, "true" outputs disable HIGH and "complementary" outputs disable LOW. If LOW, "true"
outputs disable LOW and "complementary" outputs disable HIGH.
Clock outputs
Complementary clock outputs
Reference clock select. When LOW, selects A
2
and
A
2
. When HIGH, selects A
1
and
A
1
.
Power-down control. Shuts off entire chip. If LOW, the device goes into low power mode. Inputs and outputs are disabled. Both
"true" and "complementary" outputs will pull to V
DD
. Set HIGH for normal operation.
(3)
Power supply for the device core and inputs
Power supply return for all power
No connect; recommended to connect to GND
Adjustable
(1,4)
Adjustable
(1,4)
G
1
I
LVTTL
G
2
I
LVTTL
GL
I
LVTTL
Qn
Qn
SEL
PD
O
O
I
I
LVDS
LVDS
LVTTL
LVTTL
V
DD
GND
NC
PWR
PWR
NOTES:
1. Inputs are capable of translating the following interface standards:
Single-ended 3.3V and 2.5V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL (2.5V) and LVPECL (3.3V) levels
Differential LVDS levels
Differential CML levels
2. Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to mnimze the possibility of runt
pulses or be able to tolerate themin down streamcircuitry.
3. It is recommended that the outputs be disabled before entering power-down mode. It is also recommended that the outputs remain disabled until the device completes power-
up after asserting
PD
.
4. The user must take precautions with any differential input interface standard being used in order to prevent instability when there is no input signal.
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