參數(shù)資料
型號(hào)： IDT5T2110
廠商： Integrated Device Technology, Inc.
英文描述： 2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
中文描述： 零延遲PLL 2.5V的差分時(shí)鐘驅(qū)動(dòng)器TERACLOCK
文件頁(yè)數(shù)： 16/23頁(yè)
文件大小： 162K
代理商： IDT5T2110
16
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
AC ELECTRICAL CHARACTERISTICS OV ER OPERATING RANGE
Symbol
Parameter
F
NOM
VCO Frequency Range
t
RPW
Reference Clock Pulse Width HIGH or LOW
t
FPW
Feedback Input Pulse Width HIGH or LOW
t
SK
(
O
)
Output Skew (Rise-Rise, Fall-Fall, Nomnal)
(1,2)
t
SK
1
(
ω
)
Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nomnal-Divided, Divided-Divided)
(1,2,3)
t
SK
2
(
ω
)
Multiple Frequency Skew (Rise-Fall, Nomnal-Divided, Divided-Divided)
(1,2,3)
t
SK
1
(
INV
)
Inverting Skew (Nomnal-Inverted)
(1,2)
t
SK
2
(
INV
)
Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)
(1,2,3)
t
SK
(
PR
)
Process Skew
(1,2,4)
t(
φ
)
REF Input to FB Static Phase Offset
(5)
t
ODCV
Output Duty Cycle Variation from50%
(11,12)
Min.
see VCO Frequency Range Select Table
1
—
1
—
—
—
—
—
—
—
—
—
—
—
—
—
-100
—
-375
—
-275
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
50
—
—
—
—
—
—
V
DDQ
/2 - 150
V
DDQ
/2
Typ.
Max
Unit
—
—
100
100
300
300
300
300
100
375
275
1.2
1
1.2
1
1
1
1
100
1
75
75
125
100
ns
ns
ps
ps
ps
ps
ps
ps
ps
ps
1.8V LVTTL
2.5V LVTTL
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
HSTL / eHSTL / 1.8V LVTTL
2.5V LVTTL
t
ORISE
Output Rise Time
(6)
ns
t
OFALL
Output Fall Time
(6)
ns
t
L
Power-up PLL Lock Time
(7)
PLL Lock Time After Input Frequency Change
(7)
PLL Lock Time After Asserting
PD
Pin
(7)
PLL Lock Time After Change in REF_SEL
(7,9)
PLL Lock Time After Change in REF_SEL (REF
1
and REF
0
are different frequency)
(7)
Cycle-to-Cycle Output Jitter (peak-to-peak)
(2,8)
Period Jitter (peak-to-peak)
(2,8)
Half Period Jitter (peak-to-peak)
(2,8,10)
Duty Cycle Jitter (peak-to-peak)
(2,8)
HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level
ms
ms
ms
μ
s
ms
ps
ps
ps
ps
mV
t
L
(
ω
)
t
L
(
PD
)
t
L
(
REFSEL
1
)
t
L
(
REFSEL
2
)
t
JIT
(
CC
)
t
JIT
(
PER
)
t
JIT
(
HP
)
t
JIT
(
DUTY
)
V
OX
V
DDQ
/2 + 150
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. For differential LVTTL outputs, the measurement is made at V
DDQ
/2, where the true outputs are only compared with other true outputs and the complementary outputs are only
compared to other complementary outputs. For differential HSTL/eHSTL outputs, the measurement is made at the crossing point (V
OX
) of the true and complementary signals.
3. There are three classes of outputs: nomnal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
4. t
SK
(
PR
) is the output to corresponding output skew between any two devices operating under the same conditions (V
DD
and V
DDQ
, ambient temperature, air flow, etc.).
5. t(
φ
) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken fromV
THI
on REF to V
THI
on
FB. For TxS/RxS = LOW, the measurement is taken fromthe crosspoint of REF/
REF
to the crosspoint of FB/
FB
. All outputs are set to zero delay, FB input divider is set to
divide-by-one, and FS = HIGH.
6. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
7. t
L
, t
L
(
ω
), t
L
(
REFSEL
1
), t
L
(
REFSEL
2
), and t
L
(
PD
) are the times that are required before the synchronization is achieved. These specifications are valid only after V
DD
/V
DDQ
is stable and
within the normal operating limts. These parameters are measured fromthe application of a new signal at REF or FB, or after
PD
is (re)asserted until t(
φ
) is within specified
limts.
8. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and FS = HIGH.
9. Both REF inputs must be the same frequency, but up to ±180° out of phase.
10. For HSTL/eHSTL outputs only.
11. For LVTTL outputs only.
12. t
ODCV
is measured with all outputs selected for zero delay.
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