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參數(shù)資料
| 型號(hào)： | IDT5991A-5JI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘及定時(shí) |
| 英文描述： | PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK |
| 中文描述： | 5991 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 67K |
| 代理商： | IDT5991A-5JI |
1
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT5991A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK
AUGUS T 2001
2001 Integrated Device Technology, Inc.
DSC 5843/1
c
IDT5991A
COMMERCIAL AND INDUS T RIAL T EMPERAT URE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 100MHz
2x, 4x, 1/2, and 1/4 outputs
5V with TTL outputs
3 skew grades:
IDT5991A-2: t
SKEW0
<250ps
IDT5991A-5: t
SKEW0
<500ps
IDT5991A-7: t
SKEW0
<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA I
OL
high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50
terminated lines
Pin-compatible with Cypress CY7B991
Available in PLCC Package
FUNCTIONAL BLOCK DIAGRAM
GND/sOE
1Q
0
Skew
Select
1Q
1
1F1:0
3
3
2Q
0
Skew
Select
2Q
1
2F1:0
FS
3
REF
PLL
FB
3
3Q
0
Skew
Select
3Q
1
3F1:0
3
3
4Q
0
4Q
1
Skew
Select
4F1:0
3
3
3
V
CCQ
/PE
DESCRIPTION:
The IDT5991A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5991A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The IDT5991A maintains Cypress CY7B991 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/
sOE
),
and Positive/Negative Edge Synchronization (V
CCQ
/PE). When the GND/
sOE
pin is held low, all the outputs are synchronously enabled (CY7B991
compatibility). However, if GND/
sOE
is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the V
CCQ
/PE is held high, all the outputs are syn-
chronized with the positive edge of the REF clock input (CY7B991 com-
patibility). When V
CCQ
/PE is held low, all the outputs are synchronized
with the negative edge of REF.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT5991A-7JGI | 功能描述:IC CLK DVR PLL FANOUT 32-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱(chēng):844S012AKI-01LFT |
| IDT5991A-7JGI8 | 功能描述:IC CLK DVR PLL FANOUT 32-PLCC RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類(lèi)型:時(shí)鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類(lèi)型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤(pán) 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱(chēng):844S012AKI-01LFT |
| IDT5991A-7JI | 制造商:Integrated Device Technology Inc 功能描述: |
| IDT59920A-5SOI | 制造商:MAJOR 功能描述: |
| IDT5992A2J | 制造商:Integrated Device Technology Inc 功能描述: |
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