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參數(shù)資料
| 型號： | IDT59910A-5SOI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | Scan Test Devices With 18-Bit Bus Transceivers 56-SSOP -40 to 85 |
| 中文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁數(shù)： | 2/6頁 |
| 文件大?。?/td> | 52K |
| 代理商： | IDT59910A-5SOI |
2
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT59910A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
PIN CONFIGURATION
NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
ABSOLUTE MAX IMUM RATINGS
(1)
Symbol
Description
Supply Voltage to Ground
V
I
DC Input Voltage
MaximumPower Dissipation (T
A
= 85°C)
T
STG
Storage Temperature
Max
Unit
V
V
mW
°C
–0.5 to +7
–0.5 to +7
530
–65 to +150
NOTE:
1. Capacitance applies to all inputs except TEST and FS. It is characterized but not
production tested.
CAPACITANCE
(T
A
= +25°C, f = 1MHz, V
IN
= 0V)
Parameter
Description
C
IN
Input Capacitance
Typ.
5
Max.
7
Unit
pF
PIN DESCRIPTION
Pin Name
REF
FB
TEST
(1)
GND/
sOE
(1)
Type
IN
IN
IN
IN
Description
Reference Clock Input
Feedback Input
When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Set LOW for normal operation.
Synchronous Output Enable. When HIGH, it stops clock outputs (except Q
2
and Q
3
) in a LOW state - Q
2
and Q
3
may be used as the
feedback signal to maintain phase lock. Set GND/
sOE
LOW for normal operation.
Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.
Frequency range select. 3 level input.
FS = GND: 15 to 35MHz
FS = MID (or open): 25 to 60MHz
FS = V
CC
: 40 to 100MHz
Eight clock output
Power supply for output buffers
Power supply for phase locked loop and other internal circuitry
Ground
V
CCQ
/PE
IN
FS
(2)
IN
Q
0
- Q
7
V
CCN
V
CCQ
GND
OUT
PWR
PWR
PWR
SOIC
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
REF
V
CCQ
FS
NC
V
CCQ
/PE
V
CCN
Q
0
Q
1
GND
Q
2
Q
3
V
CCN
GND
TEST
NC
GND/sOE
V
CCN
Q
7
Q
6
GND
Q
5
Q
4
V
CCN
FB
NOTES:
1. When TEST = MID and GND/
sOE
= HIGH, PLL remains active.
2. This input is wired to Vcc, GND, or unconnected. Default is MID level. If it is switched in the real time mode, the outputs may glitch, and the PLL may require an additional
lock time before all data sheet limts are achieved.
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參數(shù)描述 |
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