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參數(shù)資料
| 型號： | IDT59910A-5SOI8 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24 |
| 封裝： | 0.300 INCH, SOIC-24 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 52K |
| 代理商： | IDT59910A-5SOI8 |
1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT59910A
LOW SKEW PLL CLOCK DRIVER TURBOCLOCK JR.
SEPTEMBER 2001
2001
Integrated Device Technology, Inc.
DSC 5845/1
c
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Eight zero delay outputs
Selectable positive or negative edge synchronization
Synchronous output enable
Output frequency: 15MHz to 100MHz
TTL outputs
3 skew grades:
IDT59910A-2: tSKEW0<250ps
IDT59910A-5: tSKEW0<500ps
IDT59910A-7: tSKEW0<750ps
3-level inputs for PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA IOL high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50
terminated lines
Pin-compatible with Cypress CY7B9910
Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
G ND/sO E
Q0
Q1
REF
FS
PLL
FB
V CCQ/PE
Q2
Q3
Q4
Q5
Q6
Q7
IDT59910A
LOW SKEW
PLL CLOCK DRIVER
TURBOCLOCK JR.
DESCRIPTION:
The IDT59910A is a high fanout phase lock loop clock driver in-
tended for high performance computing and data-communications appli-
cations. The IDT59910A has eight zero delay TTL outputs.
The IDT59910A maintains Cypress CY7B9910 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (VCCQ/PE). When the GND/
sOE pin is held low, all the outputs are synchronously enabled (CY7B9910
compatibility). However, if GND/sOE is held high, all the outputs except
Q2 and Q3 are synchronously disabled.
Furthermore, when the VCCQ/PE is held high, all the outputs are syn-
chronized with the positive edge of the REF clock input (CY7B9910
compatibility). When VCCQ/PE is held low, all the outputs are synchro-
nized with the negative edge of REF.
The FB signal is compared with the input REF signal at the phase
detector in order to drive the VCO. Phase differences cause the VCO of
the PLL to adjust upwards or downwards accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
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| IDT5991A-5JGI | 功能描述:IC CLK DVR PLL FANOUT 32-PLCC RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發(fā)生器，PLL，頻率合成器 系列:TurboClock™ 標(biāo)準(zhǔn)包裝:1,000 系列:- 類型:時鐘/頻率合成器，扇出分配 PLL:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 除法器/乘法器:- 電源電壓:- 工作溫度:- 安裝類型:表面貼裝 封裝/外殼:56-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:56-VFQFP-EP（8x8） 包裝:帶卷 (TR) 其它名稱:844S012AKI-01LFT |
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