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參數(shù)資料
| 型號(hào)： | IDT5992A-7JI |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQCC32 |
| 封裝： | PLASTIC, LCC-32 |
| 文件頁(yè)數(shù)： | 1/8頁(yè) |
| 文件大?。?/td> | 67K |
| 代理商： | IDT5992A-7JI |
1
COMMERCIALANDINDUSTRIALTEMPERATURERANGES
IDT5992A
PROGRAMMABLESKEWPLLCLOCKDRIVERTURBOCLOCK
AUGUST 2001
2001
Integrated Device Technology, Inc.
DSC 5391/1
c
IDT5992A
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCK
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
4 pairs of programmable skew outputs
Low skew: 200ps same pair, 250ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Output frequency: 3.75MHz to 100MHz
2x, 4x, 1/2, and 1/4 outputs
5V with CMOS outputs
3 skew grades:
IDT5992A-2: tSKEW0<250ps
IDT5992A-5: tSKEW0<500ps
IDT5992A-7: tSKEW0<750ps
3-level inputs for skew and PLL range control
PLL bypass for DC testing
External feedback, internal loop filter
46mA IOL high drive outputs
Low Jitter: <200ps peak-to-peak
Outputs drive 50
terminated lines
Pin-compatible with Cypress CY7B992
Available in PLCC Package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT5992A is a high fanout PLL based clock driver intended for
high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5992A has eight programmable skew
outputs in four banks of 2. Skew is controlled by 3-level input signals
that may be hard-wired to appropriate HIGH-MID-LOW levels.
The IDT5992A maintains Cypress CY7B992 compatibility while pro-
viding two additional features: Synchronous Output Enable (GND/sOE),
and Positive/Negative Edge Synchronization (VDDQ/PE). When the GND/
sOE pin is held low, all the outputs are synchronously enabled (CY7B992
compatibility). However, if GND/sOE is held high, all the outputs except
3Q0 and 3Q1 are synchronously disabled.
Furthermore, when the VDDQ/PE is held high, all the outputs are syn-
chronized with the positive edge of the REF clock input (CY7B992 com-
patibility). When VDDQ/PE is held low, all the outputs are synchronized
with the negative edge of REF.
G ND/s O E
1Q 0
Ske w
Se le ct
1Q 1
1F 1:0
3
2Q 0
Ske w
Se le ct
2Q 1
2F 1:0
FS
3
RE F
PL L
FB
3
3Q 0
Ske w
Se le ct
3Q 1
3F 1:0
3
4Q 0
4Q 1
Ske w
Se le ct
4F 1:0
3
V DD Q /P E
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