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參數(shù)資料
| 型號： | IDT54FCT833APB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS PARITY BUS TRANSCEIVER |
| 中文描述： | 快速CMOS奇偶總線收發(fā)器 |
| 文件頁數(shù)： | 6/8頁 |
| 文件大?。?/td> | 71K |
| 代理商： | IDT54FCT833APB |
7.21
6
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
IDT54/74FCT833A
Com’l.
Min.
(2)
Max.
IDT54/74FCT833B
Com’l.
Min.
(2)
Max.
Mil.
Mil.
Symbol
Parameter
Conditions
(1)
Min.
(2)
Max.
Min.
(2)
Max.
Unit
t
PLH
Propagation Delay
C
L
= 50pF
C
L
= 300pF
(3)
—
10.0
—
14.0
—
7.0
—
10.0
ns
t
PHL
R
I
to T
I
, T
I
to R
I
—
17.5
—
21.5
—
14.5
—
17.5
t
PLH
Propagation Delay
C
L
= 50pF
C
L
= 300pF
(3)
—
15.0
—
20.0
—
10.5
—
14.0
ns
t
PHL
R
I
to PARITY
—
22.5
—
27.5
—
18.0
—
21.5
t
PZH
Output Enable Time
C
L
= 50pF
C
L
= 300pF
(3)
—
12.0
—
16.0
—
8.5
—
11.0
ns
t
PZL
OE
R
,
OE
T
to R
I
, T
I
Output Disable Time C
L
= 5pF
(3)
—
19.5
—
23.5
—
16.0
—
18.5
t
PHZ
—
10.7
—
14.7
—
7.2
—
9.8
ns
t
PLZ
OE
R
,
OE
T
to R
I
, T
I
C
L
= 50pF
—
12.0
—
16.0
—
8.5
—
11.0
t
SU
T
I
, PARITY to CLK
Set-up Time
C
L
= 50pF
12.0
—
16.0
—
8.5
—
11.0
—
ns
t
H
T
I
, PARITY to CLK
Hold Time
0
—
0
—
0
—
0
—
ns
t
REM
Clear Recovery Time
CLR
to CLK
15.0
—
20.0
—
10.5
—
14.0
—
ns
t
W
Clock Pulse Width
HIGH or LOW
7.0
—
9.5
—
5.5
—
7.0
—
ns
t
W
Clear Pulse Width
LOW
7.0
—
9.5
—
5.5
—
7.0
—
ns
t
PHL
Propagation Delay
CLK to
ERR
—
12.0
—
16.0
—
8.5
—
11.0
ns
t
PLH
Propagation Delay
CLR
to
ERR
—
16.0
—
20.0
—
15.0
—
18.0
ns
t
PLH
Propagation Delay
C
L
= 50pF
C
L
= 300pF
(3)
—
15.0
—
20.0
—
10.5
—
14.0
ns
t
PHL
OE
R
to PARITY
—
22.5
—
27.5
—
18.0
—
21.5
NOTES:
1. See test circuit and waveforms.
2. Minimum limits are guaranteed but not tested on Propagation Delays.
3. These parameters are guaranteed but not tested.
2557 tbl 08
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