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參數(shù)資料
| 型號： | IDT54FCT833APB |
| 廠商： | Integrated Device Technology, Inc. |
| 英文描述： | FAST CMOS PARITY BUS TRANSCEIVER |
| 中文描述： | 快速CMOS奇偶總線收發(fā)器 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大小： | 71K |
| 代理商： | IDT54FCT833APB |
7.21
2
IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
MILITARY AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
DIP/SOIC/CERPACK
TOP VIEW
LCC
TOP VIEW
2557 tbl 01
PIN DESCRIPTION
Pin Name
OE
R
I/O
I
I/O
O
Description
RECEIVE enable input.
8-bit RECEIVE data input/output.
Output from fault registers. Register
detection of odd parity fault on rising clock
edge (CLK). A registered
ERR
output
remains LOW until cleared. Open drain
output, requires pull up resistor.
Clears the fault register output.
8-bit TRANSMIT data input/output.
1-bit PARITY output.
TRANSMIT enable input.
External clock pulse input for fault register
flag.
R
I
ERR
CLR
I
T
I
PARITY
OE
T
I/O
I/O
I
I
CLK
ERROR FLAG OUTPUT FUNCTION TABLE
(1,2)
Internal
Output
Inputs
To Device
Pre-State
CLR
CLK
Point “P”
ERR
n–1
Output
ERR
Function
H
H
H
L
↑
↑
↑
—
H
—
L
—
H
L
—
—
H
L
L
H
Sample
(1’s
Capture)
Clear
NOTES:
1.
OE
T
is HIGH and
OE
R
is LOW.
2. H = HIGH
L = LOW
↑
= LOW-to-HIGH transition of clock
– = Don't Care or Irrelevant
2557 tbl 02
5
6
7
8
9
10
11
12
GND
R
1
R
2
R
3
R
4
R
5
R
6
R
7
1
2
3
4
24
23
22
21
20
19
18
17
16
15
14
13
Vcc
T
0
OE
P24-1,
D24-1,
S024-2
&
E24-1
T
1
T
2
T
3
T
4
T
5
T
6
T
7
CLK
CLR
OE
ERR
PARITY
T
R
R
0
5
6
7
8
9
10
11
L28-1
25
24
23
22
21
20
19
12 13 14 15 16 17 18
4
3
2
1
28 27 26
INDEX
2557 drw 02
R
2
R
3
R
4
NC
R
5
R
6
R
7
T
2
T
3
T
4
NC
T
5
T
6
T
7
R
1
V
O
T
1
T
0
R
R
0
N
G
C
C
O
E
P
T
N
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| IDT54FCT833BD | FAST CMOS PARITY BUS TRANSCEIVER |
| IDT54FCT833BDB | FAST CMOS PARITY BUS TRANSCEIVER |
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