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參數(shù)資料
| 型號(hào)： | IDT23S08T-3DC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | 2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| 中文描述： | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁(yè)數(shù)： | 3/6頁(yè) |
| 文件大?。?/td> | 58K |
| 代理商： | IDT23S08T-3DC |
3
COMMERCIAL TEMPERATURE RANGE
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
S2
L
L
H
H
S1
L
H
L
H
CLK A
Tri-State
Driven
Driven
Driven
CLK B
Tri-State
Tri-State
Driven
Driven
Output Source
PLL
PLL
REF
PLL
PLL Shut Down
Y
N
Y
N
FUNCTION TABLE
(1)
S ELECT INPUT DECODING
NOTE:
1. H = HIGH Voltage Level
L = LOW Voltage Level
S PR E AD S PE CT RUM COMPAT IBLE
Many systems being designed now use a technology called Spread SpectrumFrequency Timng Generation. This product is designed not to filter
off the Spread Spectrumfeature of the reference input, assumng it exists. When a zero delay buffer is not designed to pass the Spread Spectrumfeature
through, the result is a significant amount of tracking skew, which may cause problems in systems requiring synchronization.
Device
IDT23S08T-1
IDT23S08T-2
(1)
IDT23S08T-2
(1)
IDT23S08T-3
(1)
IDT23S08T-3
(1)
IDT23S08T-4
(1)
IDT23S08T-5
(1)
Feedback From
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
2 x Reference
2 x Reference
4 x Reference
2 x Reference
Reference/2
Bank B Frequency
Reference
Reference/2
Reference
Reference or
Reference
(2)
2 x Reference
2 x Reference
Reference/2
NOTES:
1. Contact factory for availability.
2. Output phase is indetermnant (0° or 180° frominput clock).
AVAILABLE OPTIONS FOR IDT23S08T
ZERO DELAY AND SK EW CONTROL
To close the feedback loop of the IDT23S08T, the FBK pin can be driven fromany of the eight available output pins. The output driving the FBK pin
will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust
the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are
loaded equally, for zero output-output skew.
NOTE:
1. Applies to both REF and FBK.
Symbol
V
DD
T
A
C
L
C
IN
Parameter
Test Conditions
Min.
2.3
0
—
—
Max.
2.7
70
15
7
Unit
V
°
C
pF
pF
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance from10MHz to 133MHz
Input Capacitance
(1)
OPERATING CONDITIONS
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IDT23S08T-4 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-4DC | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-5 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-5DC | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S09 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT23S09 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE |
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