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參數(shù)資料
| 型號： | IDT23S08T-3DC |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | 2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| 中文描述： | 23S SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16 |
| 封裝： | SOIC-16 |
| 文件頁數(shù)： | 1/6頁 |
| 文件大?。?/td> | 58K |
| 代理商： | IDT23S08T-3DC |
1
COMMERCIAL TEMPERATURE RANGE
IDT23S08T
2.5V ZERO DELAY CLOCK MULTIPLIER
NOV EMBER 2003
2003 Integrated Device Technology, Inc.
DSC - 6510/4
c
COMME RCIAL T E MPE RAT URE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 133MHz operating frequency
Distributes one clock input to two banks of four outputs
Separate output enable for each output bank
External feedback (FBK) pin is used to synchronize the outputs
to the clock input
Output Skew <200 ps
Low jitter <200 ps cycle-to-cycle
1/2x, 1x, 2x, 4x output options (see table):
– IDT23S08T-1 1x
– IDT23S08T-2 1x, 2x
– IDT23S08T-3 2x, 4x
– IDT23S08T-4 2x
– IDT23S08T-5 1/2x
No external RC network required
Operates at 2.5V V
DD
Spread spectrum compatible
Available in SOIC package
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT23S08T is a high-speed phase-lock loop (PLL) clock multiplier. It
is designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incomng
clock and the output clock, operable within the range of 10 to 133MHz.
The IDT23S08T has two banks of four outputs each that are controlled via
two select addresses. By proper selection of input addresses, both banks can
be put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for systemtesting purposes. In the absence of an
input clock, the IDT23S08T enters power down. In this mode, the device will
draw less than 12μA, and the outputs are tri-stated.
The IDT23S08T is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08T is characterized for Commercial operation.
IDT23S08T
ADVANCE
INFORMATION
2.5V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
PLL
S1
2
14
15
3
CLKA1
CLKA2
CLKA3
CLKA4
6
10
11
CLKB1
CLKB2
CLKB3
CLKB4
9
FBK
16
(-3, -4)
2
Control
Logic
7
8
1
REF
S2
(-2, -3)
2
(-5)
2
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IDT23S08T-4 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-4DC | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-5 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S08T-5DC | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:2.5V ZERO DELAY CLOCK MULTIPLIER, SPREAD SPECTRUM COMPATIBLE |
| IDT23S09 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:IDT23S09 3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE |
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