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參數(shù)資料
| 型號： | ICSSSTUA32S865AH-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, BGA-160 |
| 文件頁數(shù)： | 4/17頁 |
| 文件大?。?/td> | 199K |
| 代理商： | ICSSSTUA32S865AH-T |
12
ICSSSTUA32S865A
1053A—03/21/05
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted)
Symbol
Parameter
Measurement
Conditions
MIN
MAX
Units
fmax
Max input clock frequency
410
MHz
tPDM
Propagation delay, single
bit switching
CK
↑ to CK#↓ QN
1.25
1.9
ns
tLH
Low to High propagation
delay
CK
↑ to CK#↓ to
PTYERR#
1.2
3
ns
tHL
High to low propagation
delay
CK
↑ to CK#↓ to
PTYERR#
13
ns
tPDMSS
Propagation delay
simultaneous switching
CK
↑ to CK#↓ QN
2
ns
tPHL
High to low propagation
delay
Reset#
↓ to QN↓
3ns
tPLH
Low to High propagation
delay
Reset#
↓ to PTYERR#↑
3ns
1. Guaranteed by design, not 100% tested in production.
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted)
MIN
MAX
fclock
Clock frequency
410
MHz
tW
Pulse duration
1
ns
tACT
Differential inputs active time
10
ns
tINACT
Differential inputs inactive time
15
ns
tS
Data before CLK
↑, CLK#↓
0.5
DCS0, DSC1# before CK
↑,
CK#
↓, CSR# high
0.7
Hold time
DCS#, DODT, DCKE and Q
after CK
↑, CK#↓
0.50
ns
Hold time
PAR_IN after CK
↑, CK#↓
0.50
ns
1 - Guaranteed by design, not 100% tested in production.
2 - For data signal input slew rate of 1V/ns.
4 - CLK/CLK# signal input slew rate of 1V/ns.
SYMBOL
Notes:
tH
3 - For data signal input slew rate of 0.5V/ns and < 1V/ns.
VDD = 1.8V ±0.1V
UNITS
PARAMETERS
ns
Setup time
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