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參數(shù)資料
| 型號： | ICSSSTUA32S865AH-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| 封裝： | 9 X 13 MM, BGA-160 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大小： | 199K |
| 代理商： | ICSSSTUA32S865AH-T |
9
ICSSSTUA32S865A
1053A—03/21/05
Figure 6 — RESET# switches fr om H to L
(1) After RESET# is switched from HIGH to LOW , all data and cloc input signal must be set and held at valid logic
levels (not floating) for a minimum tim of tINACT (max.).
CK (1)
DCSn#
RESET#
tINACT
tRPHL
RESET# to Q
PARIN (1)
tRPLH
RESET# to PTYERR#
PTYERR#
H, L, or X
H or L
CK# (1)
Dn (1)
Qn
002aaa985
Register Timing
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