- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67710 > ICSSSTUA32866BHLFT SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 PDF資料下載
參數(shù)資料
| 型號(hào)： | ICSSSTUA32866BHLFT |
| 元件分類： | 鎖存器 |
| 英文描述： | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| 封裝： | 5.50 X 13.50 MM, LEAD FREE, MO-205, LFBGA-96 |
| 文件頁數(shù)： | 16/27頁 |
| 文件大?。?/td> | 307K |
| 代理商： | ICSSSTUA32866BHLFT |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁當(dāng)前第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
23
ICSSSTUA32866B
1054A—01/28/05
Notes: 1. CL incluces probe and jig capacitance.
2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA.
3. All input pulses are supplied by generators having the following chareacteristics: PRR
≤10 MHz,
Zo=50
, input slew rate = 1 V/ns ±20% (unless otherwise specified).
4. The outputs are measured one at a time with one transition per measurement.
5. VREF = VDD/2
6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input.
7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input.
8. VID = 600 mV
9. tPLH and tPHL are the same as tPDM.
Figure 6 — Parameter M easurement I nfor mation (VDD = 1.8 V ± 0.1 V)
RL =1000
CL =30 pF
(see Note 1)
LOAD CIRCUIT
tw
VICR
Inpu t
VIH
VIL
VOLTAGE WAVEFORMS – PULSE DURATION
VREF
Inpu t
tsu
th
VID
VICR
VOLTAGE WAVEFORMS – SETUP AND HOLD TIMES
VICR
VID
VICR
Ou tput
VOL
VOH
VTT
tPHL
tPLH
VOLTAGE WAVEFORMS – PROPAGATION DELA
TIMES
tRPHL
VOL
VOH
VIL
VIH
Ou tput
VOLTAGE WAVEFORMS – PROPAGATION DELA
TIMES
VDD/2
VTT
tact
tin act
LVCMOS
Input
RST#
VOLTAGE AND CURRENT WAVEFORMS
IDD
(see
Note 2)
90%
10%
INPUTS ACTIVE AND INACTIVE TIMES
0 V
VDD
Test Point
VDD/2
VCMOS
Inp ut
RST#
TL=350p s, 50
DUT
CK#
Out
TL=50
CK Inputs
VID
CK
RL =100
CK
Test Point
RL =1000
VDD
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ICSSSTUA32S865AH-T | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| ICSSSTUA32S865AHLF-T | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA160 |
| ICSSSTUB32871AHMLFT | 32871 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| ICSSSTUF32864AYH-T | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| ICSSSTUF32864AYHLF-T | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICSSSTUA32S869B | 制造商:ICS 制造商全稱:ICS 功能描述:14-Bit Configurable Registered Buffer for DDR2 |
| ICSSSTUAF32865A | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32865AHLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866B | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
| ICSSSTUAF32866BHLFT | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。