參數(shù)資料
型號(hào): ICS98ULPA877AH-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: 98ULPA SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA52
封裝: PLASTIC, MO-205, M0-225, VFBGA-52
文件頁(yè)數(shù): 1/14頁(yè)
文件大?。?/td> 159K
代理商: ICS98ULPA877AH-T
Integrated
Circuit
Systems, Inc.
ICS98ULPA877A
Advance Information
1177D—11/9/07
1.8V Low-Power Wide-Range Frequency Clock Driver
Pin Configuration
40-Pin MLF
Recommended Application:
DDR2 Memory Modules / Zero Delay Board Fan Out
Provides complete DDR2 DIMM logic solution
Product Description/Features:
Low skew, low jitter PLL clock driver
1 to 10 differential clock distribution (SSTL_18)
Feedback pins for input to output synchronization
Spread Spectrum tolerant inputs
Auto PD when input signal is at a certain logic state
Switching Characteristics:
Period jitter: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
Half-period jitter: 60ps (DDR2-400/533)
50ps (DDR2-667/800)
OUTPUT - OUTPUT skew: 40ps (DDR2-400/533)
30ps (DDR2-667/800)
CYCLE - CYCLE jitter 40ps
52-Ball BGA
Top View
Block Diagram
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
FBOUTT
FBOUTC
FBIN_INT
FBIN_INC
PLL
CLK_INT
CLK_INC
POWER
DOWN
AND
TEST
MODE
LOGIC
LD
AVDD
OE
OS
LD or OE
LD, OS, or OE
PLL BYPASS
10K
Ω -100KΩ
CLKT0
CLKC0
CLKT1
CLKC1
CLKT2
CLKC2
CLKT3
CLKC3
CLKT4
CLKC4
CLKT5
CLKC5
CLKT6
CLKC6
CLKT7
CLKC7
CLKT8
CLKC8
CLKT9
CLKC9
(1)
NOTE:
1. The Logic Detect (LD) powers down the device
when a logic LOW is applied to both CLK_INT and
CLK_INC.
B
C
D
E
F
G
H
J
K
A
12
3
4
5
6
V
D
Q
4
0
3
9
3
8
3
7
3
6
3
5
3
4
3
2
3
1
V
D
Q
1
2
1
3
1
4
1
5
1
6
1
7
1
8
1
9
2
0
V
D
Q
V
D
Q
VDDQ
FB_INT
FB_INC
FBOUTC
30
29
28
27
26
25
24
23
22
21
FBOUTT
OE
OS
VDDQ
GND
VDDQ
AGND
AVDD
CLK_INT
CLK_INC
VDDQ
2
3
4
5
6
7
8
1
9
10
VDDQ
CLKC2
CLKT2
CLKC7
CLKT7
C
L
K
C
3
C
L
K
T
3
C
L
K
C
4
C
L
K
T
4
C
L
K
C
9
C
L
K
T
9
C
L
K
C
8
C
L
K
T
8
C
L
K
C
1
C
L
K
T
1
C
L
K
C
0
C
L
K
T
0
C
L
K
C
5
C
L
K
T
5
C
L
K
C
6
C
L
K
T
6
123
45
6
A
CLKT1
CLKT0
CLKC0
CLKC5
CLKT5
CLKT6
B
CLKC1
GND
CLKC6
C
CLKC2
GND
NB
GND
CLKC7
D
CLKT2
VDDQ
OS
CLKT7
E
CLK_INT
VDDQ
NB
VDDQ
FB_INT
F
CLK_INC
VDDQ
NB
OE
FB_INC
G
AGND
VDDQ
FB_OUTC
H
AVDD
GND
NB
GND
FB_OUTT
J
CLKT3
GND
CLKT8
K
CLKC3
CLKC4
CLKT4
CLKT9
CLKC9
CLKC8
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