參數(shù)資料
型號: ICS954119
英文描述: Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
中文描述: 可編程定時控制中心⑩處理器的下一代?、?/td>
文件頁數(shù): 14/17頁
文件大小: 217K
代理商: ICS954119
14
Integrated
Circuit
Systems, Inc.
ICS954119
Advance Information
0875—05/24/04
Electrical Characteristics - SRC/SATA/PCIEX 0.7V Current Mode Differential Pair
PARAMETER
SYMBOL
CONDITIONS*
Current Source Output
Impedance
Voltage High
VHigh
Voltage Low
VLow
Max Voltage
Vovs
Min Voltage
Vuds
Crossing Voltage (abs)
Vx(abs)
Variation of crossing over all
edges
Long Accuracy
ppm
see Tperiod min-max values
100.00MHz nominal
100.00MHz spread
Absolute min period
Tabsmin
100.00MHz nominal/spread
Rise Time
t
r
V
OL
= 0.175V, V
OH
= 0.525V
Fall Time
t
f
V
OH
= 0.525V V
OL
= 0.175V
Rise Time Variation
d-t
r
V
OL
= 0.175V, V
OH
= 0.525V
Fall Time Variation
d-t
f
V
OH
= 0.525V V
OL
= 0.175V
Measurement from differential
wavefrom
Skew
t
sk3
V
T
= 50%
Measurement from differential
wavefrom
*T
A
= 0 - 70°C; V
DD
= 3.3 V +/-5%; C
L
=2pF, R
S
=33.2
, R
P
=49.9
, Ι
REF
= 475
1
Guaranteed by design and characterization, not 100% tested in production.
MIN
TYP
MAX
UNITS
Notes
Zo
V
O
= V
x
3000
1
660
-150
850
150
1150
mV
mV
mV
mV
mV
1,3
1,3
1
1
1
-300
250
550
Crossing Voltage (var)
d-Vx
140
mV
1
-300
9.9970
9.9970
9.8720
175
175
300
ppm
ns
ns
ns
ps
ps
ps
ps
1,2
2
2
1,2
1
1
1
1
10.0030
10.0533
700
700
125
125
Duty Cycle
d
t3
45
55
%
1
250
ps
1
Jitter, Cycle to cycle
t
jcyc-cyc
125
ps
1
2
All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at 14.31818MHz
3
I
REF
= V
DD
/(3xR
R
). For R
R
= 475
(1%), I
REF
= 2.32mA. I
OH
= 6 x I
REF
and V
OH
= 0.7V @ Z
O
=50
.
Average period
Tperiod
Statistical measurement on
single ended signal
Measurement on single ended
signal using absolute value.
Electrical Characteristics - PCICLK/PCICLK_F
PARAMETER
SYMBOL
Output Impedance
Output High Voltage
Output Low Voltage
CONDITIONS*
V
O
= V
DD
*(0.5)
I
OH
= -1 mA
I
OL
= 1 mA
V
OH
@MIN = 1.0 V
V
OH
@MAX = 3.135 V
V
OL
@ MIN = 1.95 V
V
OL
@ MAX = 0.4 V
Rising/Falling edge rate
V
OL
= 0.4 V, V
OH
= 2.4 V
V
OH
= 2.4 V, V
OL
= 0.4 V
V
T
= 1.5 V
V
T
= 1.5 V
V
T
= 1.5 V
MIN
12
2.4
TYP
MAX
55
UNITS
V
V
mA
mA
mA
mA
V/ns
ns
ns
%
ps
ps
NOTES
1
1
1
1
1
1
1
1
1
1
1
1
1
R
DSP
V
OH
V
OL
0.55
-33
-33
30
38
4
2
2
55
500
250
Edge Rate
Rise Time
Fall Time
Duty Cycle
Group Skew
Jitter, Cycle to cycle
*TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5%, CL = 20 pF with Rs = 7
(unless otherwise specified)
1
Guaranteed by design and characterization, not 100% tested in production.
t
slewr/f
t
r
t
f
d
t1
t
skew
t
jcyc-cyc
1
0.5
0.5
45
Output High Current
I
OH
Output Low Current
I
OL
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