參數(shù)資料
型號: ICS952802
英文描述: Programmable Timing Control Hu for P4 processor
中文描述: 可編程定時控制胡錦濤為P4處理器
文件頁數(shù): 3/19頁
文件大?。?/td> 184K
代理商: ICS952802
3
Integrated
Circuit
Systems, Inc.
ICS952802
Advance Information
0731—09/18/02
Pin Description
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1
2
3
4
5
6
7
8
9
10
11
VDDREF
PWR
I/O
I/O
I/O
PWR
IN
OUT
PWR
OUT
OUT
PWR
Ref, XTAL power supply, nominal 3.3V
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Frequency select latch input pin / 14.318 MHz reference clock.
Ground pin for the REF outputs.
Crystal input,nominally 14.318MHz.
Crystal output, nominally 14.318MHz.
Ground pin for the ZCLK outputs
3.3V Hyperzip clock output.
3.3V Hyperzip clock output.
Power supply for ZCLK clocks, nominal 3.3V
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low. This
input is selected by IIC.
Frequency select latch input pin / 3.3V PCI free running clock output.
Frequency select latch input pin / 3.3V PCI free running clock output.
Power supply for PCI clocks, nominal 3.3V
Ground pin for the PCI outputs
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
PCI clock output.
Ground pin for the PCI outputs
Power supply for PCI clocks, nominal 3.3V
*FS0/REF0
**FS1/REF1
**FS2/REF2
GNDREF
X1
X2
GNDZ
ZCLK0
ZCLK1
VDDZ
12
*PCI_STOP#/PCICLK8
I/O
13
14
15
16
17
18
19
20
21
22
23
24
**FS3/PCICLK_F0
**FS4/PCICLK_F1
VDDPCI
GNDPCI
PCICLK0
PCICLK1
PCICLK2
PCICLK3
PCICLK4
PCICLK5
GNDPCI
VDDPCI
I/O
I/O
PWR
PWR
OUT
OUT
OUT
OUT
OUT
OUT
PWR
PWR
25
PCICLK6/SEL_Reset#*
I/O
PCI clock output / Latch input pin to select pin 48 function; 0 = Reset#. 1 = CPU_Stop#
26
PCICLK7/12MHz/SELPCI_12#**
I/O
PCICLK/12MHz clock output / Latched select input for PCI/12MHz output. 0 = 12MHz,
1 = PCICLK.
Data pin for I2C circuitry 5V tolerant
Ground pin for the 48MHz outputs
24/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
24MHz.
12/48MHz clock output / Latched select input for 24/48MHz output. 0=48MHz, 1 =
12MHz.
Power for 24/48MHz outputs and fixed PLL core, nominal 3.3V
Clock pin of I2C circuitry 5V tolerant
Power supply for AGP clocks, nominal 3.3V
AGP clock output
AGP clock output
Ground pin for the AGP outputs
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
3.3V Analog Power pin for Core PLL
Analog Ground pin for Core PLL
Ground pin for the CPU outputs
"Complementary" clocks of differential 3.3V push-pull K8 pair.
"True" clocks of differential 3.3V push-pull K8 pair.
Supply for CPU clocks, 3.3V nominal
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential 3.3V push-pull K8 pair.
"True" clocks of differential 3.3V push-pull K8 pair.
Ground pin for the CPU outputs
Slectable real time CPU_Stop# (Input) or Reset# (Output)
27
28
SDATA
GND48
I/O
PWR
29
24_48MHz/SEL24_48#*~
I/O
30
12_48MHz/SEL12_48#**
I/O
31
32
33
34
35
36
AVDD48
SCLK
VDDAGP
AGPCLK1
AGPCLK0
GNDAGP
PWR
IN
PWR
OUT
OUT
PWR
37
PD#*
IN
38
39
40
41
42
43
44
45
46
47
48
AVDD
AGND
GNDCPU
CPUCLK8C0
CPUCLK8T0
VDDCPU
VDDCPU
CPUCLK8C1
CPUCLK8T1
GNDCPU
CPU_STOP#/Reset#*
* Internal Pull-Up Resistor ** Internal Pull-Down Resistor ~ This Output has 1.5X Drive Strength
PWR
PWR
PWR
OUT
OUT
PWR
PWR
OUT
OUT
PWR
I/O
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