參數(shù)資料
型號(hào)： ICS952606FLFT
英文描述： Programmable Timing Control Hub for Next Gen P4 processor
中文描述： 可編程定時(shí)控制中心，為下一代P4處理器
文件頁(yè)數(shù)： 3/20頁(yè)
文件大?。?/td> 162K
代理商： ICS952606FLFT
3
Integrated
Circuit
Systems, Inc.
ICS952606
0717F—06/10/05
Pin Description (Continued)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
30
25
26
27
28
29
30
31
32
3V66_0
3V66_3/VCH
3V66_2
VDD3V66
GND
3V66_1
3V66_0
SCLK
SDATA
OUT
OUT
OUT
PWR
PWR
OUT
OUT
IN
I/O
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output / 48MHz VCH clock output.
3.3V 66.66MHz clock output
Power pin for the 3.3V 66MHz clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Clock pin of SMBus circuitry, 5V tolerant.
Data pin for SMBus circuitry, 5V tolerant.
This 3.3V LVTTL input is a level sensitive strobe used to determine
when latch inputs are valid and are ready to be sampled. This is an
active low input.
Power supply, nominal 3.3V
Complement clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
True clock of differential pair for S-ATA support.
+/- 300ppm accuracy required.
Ground pin.
33
Vtt_Pwrgd#
IN
34
VDD
PWR
35
SRCCLKC
OUT
36
SRCCLKT
OUT
37
GND
PWR
38
CPUCLKC0
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
39
CPUCLKT0
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
40
VDDCPU
PWR
41
CPUCLKC1
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
42
CPUCLKT1
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Ground pin.
43
GND
PWR
44
CPUCLKC_ITP
OUT
Complementary clock of differential pair CPU outputs. These are
current mode outputs. External resistors are required for voltage bias.
45
CPUCLKT_ITP
OUT
True clock of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
This pin establishes the reference current for the differential current-
mode output pairs. This pin requires a fixed precision resistor tied to
ground in order to establish the appropriate current. 475 ohms is the
standard value.
Ground pin.
3.3V power for the PLL core.
46
IREF
OUT
47
48
GND
VDDA
PWR
PWR
相關(guān)PDF資料
PDF描述
ICS952607YFLF-T Circular Connector; MIL SPEC:MIL-DTL-38999 Series III; Body Material:Metal; Series:TV01; Number of Contacts:6; Connector Shell Size:9; Connecting Termination:Crimp; Circular Shell Style:Straight Receptacle; Body Style:Straight
ICS952607 16-Bit Buffers/Drivers With 3-State Outputs 48-SSOP -40 to 85
ICS952621 Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS952607 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952607YFLF-T 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for Next Gen P4 processor
ICS952620CFLF 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT
ICS952620CFLFT 功能描述:IC TIMING CTRL HUB P4 48-SSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專(zhuān)用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類(lèi)型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱(chēng):93786AFT
ICS952621 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub⑩ for Next Gen P4⑩ processor
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