參數(shù)資料
型號: ICS952606FLFT
英文描述: Programmable Timing Control Hub for Next Gen P4 processor
中文描述: 可編程定時控制中心,為下一代P4處理器
文件頁數(shù): 15/20頁
文件大?。?/td> 162K
代理商: ICS952606FLFT
15
Integrated
Circuit
Systems, Inc.
ICS952606
0717F—06/10/05
I
2
C Table: VCO Frequency Control Register
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Name
N Div7
N Div6
N Div5
N Div4
N Div3
N Div2
N Div1
N Div0
Control Function
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
I
2
C Table: Spread Spectrum Control Register
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Name
SSP7
SSP6
SSP5
SSP4
SSP3
SSP2
SSP1
SSP0
Control Function
These Spread
Spectrum bits will
program the spread
pecentage. It is
recommended to use
ICS Spread % table for
spread programming.
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
X
X
X
X
X
X
X
X
I
2
C Table: Spread Spectrum Control Register
Pin #
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
Name
Reserved
Reserved
SSP13
SSP12
SSP11
SSP10
SSP9
SSP8
Control Function
Reserved
Reserved
Type
RW
RW
RW
RW
RW
RW
RW
RW
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
X
X
X
X
X
X
Byte 14
-
-
-
-
-
-
-
It is recommended to
use ICS Spread %
table for spread
programming.
Byte 13
-
-
-
-
-
-
-
Byte 12
-
-
-
-
-
-
-
The decimal
representation of N Div
(8:0) is equal to VCO
divider value. Default
at power up = latch-in
or Byte 0 Rom table.
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