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參數(shù)資料
| 型號(hào)： | ICS952301 |
| 英文描述： | Frequency Timing Generator for Transmeta Systems |
| 中文描述： | 全美達(dá)系統(tǒng)的頻率定時(shí)發(fā)生器 |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 591K |
| 代理商： | ICS952301 |
7
ICS952301
Advance Information
0673—07/09/02
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the
ICS952301
. It is used to turn off the PCICLK clocks for low power operation.
PCI_STOP# is synchronized by the
ICS952301
internally. The minimum that the PCICLK clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK clocks. PCICLK clocks are stopped in a low state and started with a
full high pulse width guaranteed. PCICLK clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the
ICS952301
. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse)
is 100 CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be
stopped in a low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency
is less than 4 CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may
exist. This signal is synchronized to the CPUCLKs inside the
ICS9248-192
.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS952301 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS952301.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
PCICLK
CPUCLK
PCI_STOP# (High)
CPU_STOP#
PD# (High)
INTERNAL
CPUCLK
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS952301YG-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Transmeta Systems |
| ICS952302 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator for TransmetaTM |
| ICS952302AG | 功能描述:IC FREQ GENERATOR 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS952302AGT | 功能描述:IC FREQ GENERATOR 48-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:28 系列:- 類型:時(shí)鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務(wù)器 輸入:時(shí)鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應(yīng)商設(shè)備封裝:64-TSSOP 包裝:管件 |
| ICS952302YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator for TransmetaTM |
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