參數(shù)資料
型號(hào): ICS952301
英文描述: Frequency Timing Generator for Transmeta Systems
中文描述: 全美達(dá)系統(tǒng)的頻率定時(shí)發(fā)生器
文件頁數(shù): 6/12頁
文件大?。?/td> 591K
代理商: ICS952301
6
ICS952301
Advance Information
0673—07/09/02
BYTE
0
Pin #
Name
Control Function
0
1
PWD
Bit 7
-
-
Frequency select by bit 7
RW
1
Bit 6
-
-
Frequency select by bit 6
RW
1
Bit 5
-
-
Frequency select by bit 5
RW
1
Bit 4
Bit 3
Bit 2
Frequency select by bit 4
Reserved
Frequency select by bit 2
RW
R
RW
1
1
1
-
-
-
-
-
-
Bit 1
-
-
Spread Enable
RW
Normal
Enable
0
Bit 0
-
-
Output Control
RW
Running
Tri-state
0
Affected Pin
T
Bit Control
See Frequency table
See Frequency table
BYTE
1
Pin #
Name
Control Function
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
11
10
9
6
5
-
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
Output disable
Output disable
Output disable
Output disable
Output disable
Output disable
Output disable
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
1
1
1
1
1
1
1
0
Affected Pin
T
Bit Control
BYTE
2
Pin #
Name
Control Function
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
18
17
23
27
9
11
-
-
48MHz
24_48MHz
CPUCLK0
REF
PCICLK2
PCICLK4
-
-
Output Disable
Output Disable
Output disable
Output disable
1X or 2X
1X or 2X
PCI HW SEL Status
(Reserved)
RW
RW
RW
RW
RW
RW
R
-
Disable
Disable
Disable
Disable
2X
2X
2X
-
Enable
Enable
Enable
Enable
1X
1X
1X
-
1
1
1
1
1
1
1
X
Affected Pin
T
Bit Control
BYTE
3
Pin #
Name
Control Function
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
15
14
11
10
9
6
5
-
PCICLK6
PCICLK5
PCICLK4
PCICLK3
PCICLK2
PCICLK1
PCICLK0
-
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
Free Run Status
(Reserved)
RW
RW
RW
RW
RW
RW
RW
-
Disable
Disable
Disable
Disable
Disable
Disable
Disable
-
Enable
Enable
Enable
Enable
Enable
Enable
Enable
-
1
1
1
1
1
1
1
X
Affected Pin
Bit Control
T
BYTE
4
Pin #
Name
Control Function
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
Affected Pin
T
Bit Control
BYTE
5
Pin #
Name
Control Function
0
1
PWD
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
X
X
X
X
X
X
X
T
Bit Control
Affected Pin
BYTE
6
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Pin #
-
-
-
-
-
-
-
-
Name
-
-
-
-
-
-
-
-
Control Function
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
0
-
-
-
-
-
-
-
-
1
-
-
-
-
-
-
-
-
PWD
0
0
0
0
0
1
1
0
-
-
-
-
-
-
-
-
Affected Pin
T
E
Bit Control
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