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參數(shù)資料
| 型號： | ICS951402YG-T |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 210 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 6/23頁 |
| 文件大?。?/td> | 289K |
| 代理商： | ICS951402YG-T |
14
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
I
2C Table: Slew Rate Control Register
Byte 21 Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
24_48Slw1
RW
-
0
Bit 6
-
24_48Slw0
24_48 Slew Rate
Control
RW
-
0
Bit 5
-
AGPSlw1
RW
-
0
Bit 4
-
AGPSlw0
AGP Slew Rate
Control
RW
-
0
Bit 3
-
Reserved
RW
-
0
Bit 2
-
Reserved
RW
-
0
Bit 1
-
REFSlw1
RW
-
0
Bit 0
-
REFSlw0
REF Slew
Rate Control
RW
-
0
I
2C Table: Slew Rate Control Register
Byte 22 Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
SDSlw1
RW
-
0
Bit 6
-
SDSlw0
SDRAM Slew Rate
Control
RW
-
0
Bit 5
-
Reserved
RW
-
0
Bit 4
-
Reserved
RW
-
0
Bit 3
-
PCISlw1
RW
-
0
Bit 2
-
PCISlw0
PCI_F Slew Rate
Control
RW
-
0
Bit 1
-
PCISlw1
RW
-
0
Bit 0
-
PCISlw0
PCI Slew Rate
Control
RW
-
0
I
2C Table: Output Control Register
Byte 23 Pin #
Name
Control
Function
Type
0
1
PWD
Bit 7
-
Reserved
-
X
Bit 6
27
48MHz_1
Output Control
RW
Disable
Enable
1
Bit 5
47
SDRAM
Output Control
RW
Disable
Enable
1
Bit 4
28
48MHz_0
Output Control
RW
Disable
Enable
1
Bit 3
26
24_48MHz
Output Control
RW
Disable
Enable
1
Bit 2
4
REF2
Output Control
RW
Disable
Enable
1
Bit 1
3
REF1
Output Control
RW
Disable
Enable
1
Bit 0
2
REF0
Output Control
RW
Disable
Enable
1
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