- 您現(xiàn)在的位置：買賣IC網 > PDF目錄9601 > ICS951402AGLFT (IDT, Integrated Device Technology Inc)IC TIMING CTRL HUB P4 48-TSSOP PDF資料下載
參數資料
| 型號： | ICS951402AGLFT |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數： | 14/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TIMING CTRL HUB P4 48-TSSOP |
| 標準包裝： | 1,000 |
| 系列： | TCH™ |
| 類型： | 時鐘/頻率發(fā)生器，多路復用器 |
| PLL： | 是 |
| 主要目的： | Intel CPU，Timing Control Hub? |
| 輸入： | 晶體 |
| 輸出： | 時鐘 |
| 電路數： | 1 |
| 比率 - 輸入:輸出： | 1:19 |
| 差分 - 輸入:輸出： | 無/是 |
| 頻率 - 最大： | 210MHz |
| 電源電壓： | 3.135 V ~ 3.465 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TFSOP（0.240"，6.10mm 寬） |
| 供應商設備封裝： | 48-TSSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | 951402AGLFT |
21
Integrated
Circuit
Systems, Inc.
ICS951402
Advance Information
0660—05/05/05
The impact of asserting the PCI_STOP# signal will be the following. All PCI and stoppable PCI_F clocks will latch low in their
next high to low transition. The PCI_STOP# setup time tsu is 10 ns, for transitions to be recognized by the next rising edge.
PCI_STOP#
PCI_F 33MHz
PCI 33MHz
tsu
Assertion of PCI_STOP# Waveforms
PCI_STOP# - Assertion (transition from logic "1" to logic "0")
CPU_STOP#
CPUT
CPUC
The impact of asserting the CPU_STOP# pin is all CPU outputs that are set in the I
2C configuration to be stoppable via
assertion of CPU_STOP# are to be stopped after their next transition following the two CPU clock edge sampling as shown.
The final state of the stopped CPU signals is CPUT=High and CPUC=Low. There is to be no change to the output drive current
values. The CPUT will be driven high with a current value equal to (MULTSEL0) X (I REF), the CPUC signal will not be driven.
CPU_STOP# - Assertion (transition from logic "1" to logic "0")
Assertion of CPU_STOP# Waveforms
相關PDF資料 |
PDF描述 |
|---|---|
| ICL3241ECV | IC 3DRVR/5RCVR RS232 3V 28-TSSOP |
| ICL3241ECB-T | IC 3DRVR/5RCVR RS232 3V 28-SOIC |
| ICL3244ECA-T | IC 3DRVR/5RCVR RS232 3V 28-SSOP |
| GTC06AF-28-21S | CONN PLUG 37POS STRAIGHT W/SCKT |
| M83723/74W1203N | CONN RCPT 3POS JAM NUT W/PINS |
相關代理商/技術參數 |
參數描述 |
|---|---|
| ICS951402YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for P4 processor |
| ICS951402YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:Programmable Timing Control Hub for P4 processor |
| ICS951403 | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951403YFLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7 System Clock Chip |
| ICS951403YGLF-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD-K7 System Clock Chip |
發(fā)布緊急采購，3分鐘左右您將得到回復。