參數(shù)資料
型號: ICS950813YFT
英文描述: Frequency Generator with 200MHz Differential CPU Clocks
中文描述: 頻率發(fā)生器200MHz的CPU的時鐘差分
文件頁數(shù): 2/22頁
文件大?。?/td> 265K
代理商: ICS950813YFT
2
ICS950813
Advance Information
0708—10/10/02
Pin Description
PIN # PIN NAME
1
VDDREF
2
X1
3
X2
4
GND
5
PCICLK_F0
6
PCICLK_F1
PIN TYPE
PWR
IN
OUT
PWR
OUT
OUT
DESCRIPTION
Ref, XTAL power supply, nominal 3.3V
Crystal input,nominally 14.318MHz.
Crystal output, Nominally 14.318MHz
Ground pin.
Free running PCI clock not affected by PCI_STOP# .
Free running PCI clock not affected by PCI_STOP# .
Asynchronous AGP/PCI frequency latch input pin / 3.3V PCI free running
clock put. Pull-Up = Main PLL / Pull-Down = Async Fix PLL
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
Early/Normal PCI clock output latched at power up.
PCI clock output.
Early/Normal PCI clock output latched at power up.
Power supply for PCI clocks, nominal 3.3V
Ground pin.
PCI clock output.
PCI clock output.
PCI clock output.
Power pin for the 3V66 clocks.
Ground pin.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
7
*ASEL/PCICLK_F2
I/O
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDPCI
GND
PCICLK0
**E_PCICLK1/PCICLK1
PCICLK2
**E_PCICLK3/PCICLK3
VDDPCI
GND
PCICLK4
PCICLK5
PCICLK6
VDD3V66
GND
3V66_2
3V66_3
3V66_4
3V66_5
PWR
PWR
OUT
I/O
OUT
I/O
PWR
PWR
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
25
*PD#
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal
are stopped. The latency of the power down will not be greater than 3ms.
26
27
VDDA
GND
PWR
PWR
3.3V power for the PLL core.
Ground pin.
This 3.3V LVTTL input is a level sensitive strobe used to determine when
latch inputs are valid and are ready to be sampled. This is an active low
input.
28
Vtt_PWRGD#
IN
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