參數(shù)資料
型號(hào)： ICS950813
英文描述： Frequency Generator with 200MHz Differential CPU Clocks
中文描述： 頻率發(fā)生器200MHz的CPU的時(shí)鐘差分
文件頁(yè)數(shù)： 3/22頁(yè)
文件大?。?/td> 265K
代理商： ICS950813
3
ICS950813
Advance Information
0708—10/10/02
Pin Description (Continued)
PIN # PIN NAME
29
SDATA
30
SCLK
31
GND
32
VDD3V66
33
3V66_0/FS4**
PIN TYPE
I/O
IN
PWR
PWR
I/O
DESCRIPTION
Data pin for I2C circuitry 5V tolerant
Clock pin of I2C circuitry 5V tolerant
Ground pin.
Power pin for the 3V66 clocks.
Frequency select latch input pin / 3.3V 66.66MHz clock output.
Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input
low
Frequency select latch input pin / 3.3V 66.66MHz clock output / 48MHz
VCH clock output.
Ground pin.
Power for 24 & 48MHz output buffers and fixed PLL core.
48MHz clock output.
Frequency select latch input pin / 3.3V 48MHz clock output.
Real Time input pin to change frequency to under-clock entries located in
FS 4:2 = '100'. Clock groups gear ratio will not be change during this
operation.
Ground pin.
This pin establishes the reference current for the CPUCLK pairs. This pin
requires a fixed precision resistor tied to ground in order to establish the
appropriate current.
3.3V LVTTL input for selection the current multiplier for CPU outputs
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
Ground pin.
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Supply for CPU clocks, 3.3V nominal
"Complementary" clocks of differential pair CPU outputs. These are current
mode outputs. External resistors are required for voltage bias.
"True" clocks of differential pair CPU outputs. These are current mode
outputs. External resistors are required for voltage bias.
Stops all CPUCLK besides the free running clocks
Frequency select pin.
Frequency select pin.
14.318 MHz reference clock.
34
PCI_STOP#*
IN
35
3V66_1/VCH_CLK/FS3**
I/O
36
37
38
39
GND
VDD48
48MHz_DOT
48MHz_USB/FS2**
PWR
PWR
OUT
I/O
40
PWRSAVE#*
IN
41
GND
PWR
42
IREF
OUT
43
MULTSEL*
IN
44
CPUCLKC2
OUT
45
CPUCLKT2
OUT
46
47
VDDCPU
GND
PWR
PWR
48
CPUCLKC1
OUT
49
CPUCLKT1
OUT
50
VDDCPU
PWR
51
CPUCLKC0
OUT
52
CPUCLKT0
OUT
53
54
55
56
CPU_STOP#*
FS0
FS1
REF
IN
IN
IN
OUT
Power Supply
VDD
1
37
46
GND
4
36
47
Xtal, Ref, CPU PLL, digital
48MHz, Fix Digital, Fix Analog
Master clock, CPU Analog
Pin Number
Description
相關(guān)PDF資料
PDF描述
ICS950813YFT Frequency Generator with 200MHz Differential CPU Clocks
ICS950813YGT Frequency Generator with 200MHz Differential CPU Clocks
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ICS950901YFLFT TRIMMER, 500K
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
ICS950813YFT 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks
ICS950813YGT 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks
ICS950818 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks
ICS950818YG-T 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Frequency Generator with 200MHz Differential CPU Clocks
ICS950901 制造商:ICS 制造商全稱(chēng):ICS 功能描述:Programmable Timing Control Hub for P4
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