參數(shù)資料
型號(hào): ICS950805
英文描述: 16-Bit Buffers/Drivers With 3-State Outputs 48-SSOP -40 to 85
中文描述: 頻率發(fā)生器200MHz的CPU的時(shí)鐘差分
文件頁(yè)數(shù): 7/20頁(yè)
文件大?。?/td> 180K
代理商: ICS950805
7
ICS950805
0649H—02/25/05
Absolute Maximum Ratings
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . 0°C to +85°C
Case Temperature . . . . . . . . . . . . . . . . . . . . . . 115°C
Storage Temperature. . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under Absolute Maximum Ratingsmay cause permanent damage to the device. These
ratings are stress specifications only and functional operation of the device at these or any other conditions above those
listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions
for extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
T
A
= 0 - 70C; Supply Voltage V
DD
= 3.3 V +/-5%
PARAMETER
SYMBOL
Input High Voltage
V
IH
Input Low Voltage
V
IL
Input High Current
I
IH
V
IN
= V
DD
I
IL1
V
IN
= 0 V; Inputs with no pull-up resistors
Input Low Current
CONDITIONS
MIN
2
TYP
MAX
V
DD
+0.3
0.8
5
UNITS
V
V
mA
mA
V
SS
-0.3
-5
-5
I
IL2
V
IN
= 0 V; Inputs with pull-up resistors
-200
Operating Supply
Current
I
DD3.3OP
C
L
= Full load; Select @ 100 MHz
229
230
360
mA
I
DD3.3OP
C
L
=Full load; Select @ 133 MHz
IREF=5 mA
V
DD
= 3.3 V
220
233
38.1
14.318
360
45
mA
Powerdown Current
Input Frequency
Pin Inductance
I
DD3.3PD
F
i
L
pin
C
IN
C
OUT
C
INX
T
trans
T
s
T
STAB
T
1C
t
PZH
,t
PZL
t
PHZ
,t
PLZ
mA
MHz
nH
pF
pF
pF
ms
ms
ms
ms
ns
ns
7
5
6
Logic Inputs
Output pin capacitance
X1 & X2 pins
To 1st crossing of target frequency
From 1st crossing to 1% target frequency
From V
DD
= 3.3 V to 1% target frequency
Time to first clock
Output enable delay (all outputs)
Output disable delay (all outputs)
27
36
45
3
3
3
1.8
10
10
Transition time
1
Settling time
1
Clk Stabilization
1
Time to first clock
1
1
1
1
1
Guaranteed by design, not 100% tested in production.
Delay
1
Input Capacitance
1
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