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參數(shù)資料
| 型號： | ICS950227YFT |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 133.33 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO56 |
| 封裝： | 0.300 INCH, MO-118, SSOP-56 |
| 文件頁數(shù)： | 17/17頁 |
| 文件大?。?/td> | 128K |
| 代理商： | ICS950227YFT |
9
Integrated
Circuit
Systems, Inc.
ICS950227
0641D—07/03/03
I
2C Table: Output Divider Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Reserved
RW
-
0
Bit 6
Reserved
RW
-
0
Bit 5
Reserved
RW
-
0
Bit 4
CPUINV
CPU Phase Invert
RW
Default
Inverse
0
Bit 3
Reserved
RW
-
0
Bit 2
Reserved
RW
-
0
Bit 1
Reserved
RW
-
0
Bit 0
Reserved
RW
-
0
I
2C Table: Group Skew Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Reserved
RW
-
0
Bit 6
Reserved
RW
-
0
Bit 5
Reserved
RW
-
0
Bit 4
Reserved
RW
-
0
Bit 3
CPUSkw1
RW
-
0
Bit 2
CPUSkw0
RW
-
1
Bit 1
Reserved
RW
-
0
Bit 0
Reserved
RW
-
0
I
2C Table: Group Skew Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
Reserved
RW
-
0
Bit 6
Reserved
RW
-
0
Bit 5
Reserved
RW
-
0
Bit 4
Reserved
RW
-
0
Bit 3
PCISkw3
RW
0
Bit 2
PCISkw2
RW
1
Bit 1
PCISkw1
RW
0
Bit 0
PCISkw0
RW
0
I
2C Table: Slew Rate Control Register
Pin #
Name
Control Function
Type
0
1
PWD
Bit 7
3V66ISkw
RW
0
Bit 6
3V66ISkw
RW
1
Bit 5
Reserved
RW
-
0
Bit 4
Reserved
RW
-
0
Bit 3
RESERVED
Reserved
-
0
Bit 2
RESERVED
Reserved
-
0
Bit 1
RESERVED
Reserved
-
0
Bit 0
RESERVED
Reserved
-
0
16-Steps Skew Control.
This byte will advance or
delay the skew by 100ps
per step
Byte 20
-
3V66 (5:0) Skew
Control
Skew Control This byte
will advance or delay the
skew by 250 ps per step
-
PCI (6:1) AND
PCIF(2:0) Skew
Control
-
CPUCLKT/C (2:0)
Skew Control
Byte 19
-
Byte 17
-
Byte 18
-
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