參數(shù)資料
型號: ICS950219YFLF-T
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘產(chǎn)生/分配
英文描述: 200.4 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48
封裝: 0.300 INCH, MO-118, SSOP-48
文件頁數(shù): 10/19頁
文件大?。?/td> 206K
代理商: ICS950219YFLF-T
Integrated
Circuit
Systems, Inc.
ICS950219
Preliminary Product Preview
0640D—12/30/03
All 3V66 clocks are to be in pphase with each other. In the case where 3V66_1 is configured as 48MHz VCH clock, there is no
defined phase relationship between 3V66_1/VCH and other 3V66 clocks. The PCI group should lag 3V66 by the standard
skew described below as Tpci.
Un-Buffered Mode 3V66 & PCI Phase Relationship
3V66
PCICLK_F and PCICLK
Tpci
Group Skews at Common Transition Edges: (Un-Buffered Mode)
GROUP
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
3V66
3V66 pin to pin skew
0
500
ps
PCI
PCI_F and PCI pin to pin skew
0
500
ps
3V66 to PCI
S3V66-PCI
3V66 leads 33MHz PCI
1.5
3.5
ns
1Guarenteed by design, not 100% tested in production.
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