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參數(shù)資料
| 型號： | ICS94211yF-T |
| 英文描述： | Programmable System Frequency Generator for PII/III⑩ |
| 中文描述： | 可編程系統(tǒng)頻率發(fā)生器有價證券/三⑩ |
| 文件頁數(shù)： | 1/16頁 |
| 文件大小： | 359K |
| 代理商： | ICS94211YF-T |
Integrated
Circuit
Systems, Inc.
ICS94211
94211 Rev A 03/28/01
Pin Configuration
Recommended Application:
440BX/VIA Apollo Pro133/ ALI 1631 style chipset.
Output Features:
2 - CPUs @2.5V
1 - IOAPIC @ 2.5V
13 - SDRAM @ 3.3V
6 - PCI @3.3V,
1 - 48MHz, @3.3V
1 - 24MHz @ 3.3V
2 - REF @3.3V, 14.318MHz.
Features:
Programmable ouput frequency.
Programmable ouput rise/fall time.
Programmable PCICLK, PCICLK_F,
SDRAM skew.
Real time system reset output
Spread spectrum for EMI control typically by 7dB to 8dB,
with programmable spread percentage.
Watchdog timer technology to reset system
if over-clocking causes malfunction.
Uses external 14.318MHz crystal.
FS pins for frequency select
Key Specifications:
CPU – CPU: <175ps
SDRAM - SDRAM: <500ps
PCI – PCI: <500ps
CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Programmable System Frequency Generator for P
II
/
III
Block Diagram
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
** Internal Pull-down resistor of 120K to GND
VDDREF
*PCI_STOP/REF0
GND
X1
X2
VDDPCI
*MODE/PCICLK_F
**FS3/PCICLK0
GND
PCICLK1
PCICLK2
PCICLK3
PCICLK4
VDDPCI
BUFFER_IN
GND
SDRAM12
SDRAM11
VDDSDR
SDRAM10
SDRAM9
GND
SDATA
SCLK
VDDL
IOAPIC
REF1/FS2*
GND
CPUCLK0
CPUCLK1
VDDLCPU
RESET#
SDRAM0
GND
SDRAM1
SDRAM2
VDDSDR
SDRAM3
SDRAM4
GND
SDRAM5
SDRAM6
VDDSDR
SDRAM7
SDRAM8
VDD48
48MHz/FS0*
24MHz/FS1*
I
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Functionality
3
S
F
2
S
F
1
S
F
0
S
F
U
)
H
0
0
8
0
7
3
8
8
6
0
0
1
0
1
1
0
6
2
0
1
0
2
1
9
1
1
9
0
1
0
0
1
0
4
1
0
5
1
0
2
1
9
3
1
P
C
M
(
K
L
)
0
0
5
1
3
4
1
1
0
3
6
0
0
0
0
5
C
H
I
C
M
(
0
4
5
3
6
4
4
3
3
3
3
3
0
3
4
3
0
4
3
3
6
3
0
3
0
3
5
3
0
3
2
3
P
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2
0
1
1
3
0
9
9
0
0
0
0
9
PCI_STOP#
SDATA
PLL2
PLL1
Spread
Spectrum
48MHz
24MHz
IOAPIC
CPUCLK (1:0)
RESET#
SDRAM (12:0)
PCICLK (4:0)
PCICLK_F
X1
X2
BUFFER IN
XTAL
OSC
PCI
CLOCK
DIVDER
STOP
SCLK
FS(3:0)
MODE
Control
Logic
Config.
Reg.
/2
REF(1:0)
2
2
13
5
4
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
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