參數(shù)資料
型號: ICS93V855YGIT
元件分類: 時鐘及定時
英文描述: PLL BASED CLOCK DRIVER, 5 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO28
封裝: 0.173 INCH, MO-153, TSSOP-28
文件頁數(shù): 1/9頁
文件大?。?/td> 119K
代理商: ICS93V855YGIT
Integrated
Circuit
Systems, Inc.
ICS93V855I
Preliminary Product Preview
0783A—04/30/03
Block Diagram
DDR Phase Lock Loop Clock Driver
Recommended Application:
DDR Clock Driver
Product Description/Features:
Low skew, low jitter PLL clock driver
External feedback pins for input to output
synchronization
Spread Spectrum tolerant inputs
With bypass mode mux
Operating frequency 60 to 170 MHz
Operating Temperature –45°C to +85°C
Switching Characteristics:
CYCLE - CYCLE jitter:<75ps
OUTPUT - OUTPUT skew: <60ps
Output Rise and Fall Time: 650ps - 950ps
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
AVDD
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
Functionality
S
T
U
P
N
IS
T
U
P
T
U
O
e
t
a
t
S
L
P
D
V
AT
N
I
_
K
L
CC
N
I
_
K
L
CT
K
L
CC
K
L
CT
T
U
O
_
B
FC
T
U
O
_
B
F
D
N
GL
H
L
H
L
H
f
O
/
d
e
s
a
p
y
B
D
N
GH
L
H
L
H
L
f
O
/
d
e
s
a
p
y
B
V
5
.
2
)
m
o
n
(
LH
L
H
L
H
n
O
V
5
.
2
)
m
o
n
(
HL
H
L
H
L
n
O
V
5
.
2
)
m
o
n
(
z
H
M
0
2
<z
H
M
0
2
<Z
-
i
HZ
-
i
HZ
-
i
HZ
-
i
Hf
f
O
GND
1
28 DDRC4
DDRC0
2
27 DDRT4
DDRT0
3
26 VDD2.5
VDD2.5
4
25 GND
CLK_INT
5
24 FB_OUTC
CLK_INC
6
23 FB_OUTT
AVDD2.5
7
22 VDD2.5
AGND
8
21 FB_INT
GND
9
20 FB_INC
DDRC1 10
19 GND
DDRT1 11
18 VDD2.5
VDD2.5 12
17 DDRT3
DDRT2 13
16 DDRC3
DDRC2 14
15 GND
IC
S93V855I
Pin Configuration
28-Pin 4.4mm TSSOP
PRODUCT PREVIEW documents contain information on new products in the sampling or preproduction phase of development. Characteristic data and other specifications are subject to
change without notice.
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