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參數(shù)資料
| 型號： | ICS93V857YGT |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO48 |
| 封裝： | 6.10 MM, 0.50 MM PITCH, MO-153, TSSOP-48 |
| 文件頁數(shù)： | 1/9頁 |
| 文件大小： | 323K |
| 代理商： | ICS93V857YGT |
Integrated
Circuit
Systems, Inc.
ICS93V857
Preliminary Product Preview
Block Diagram
DDR Phase Lock Loop Clock Driver
93V857 Rev A 11/10/00
Pin Configuration
48-Pin TSSOP
RecommendedApplication:
DDR Memory Modules
Product Description/Features:
Low skew, low jitter PLLclock driver
1 to 10 differential clock distribution
Feedback pins for input to output synchronization
PD# for power management
Spread Spectrum tolerant inputs
Specifications:
Meet JEDEC standard #82 for registered DDR
clock driver.
Switching Characteristics:
PEAK - PEAK jitter (66MHz): <120ps
PEAK - PEAK jitter (>100MHz): <75ps
CYCLE-CYCLEjitter(66MHz):<120ps
CYCLE-CYCLEjitter(>100MHz):<65ps
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time: 650ps - 950ps
DUTYCYCLE:49.5%-50.5%
GND
CLKC0
CLKT0
VDD
CLKT1
CLKC1
GND
CLKC2
CLKT2
VDD
CLK_INT
CLK_INC
VDD
AVDD
AGND
GND
CLKC3
CLKT3
VDD
CLKT4
CLKC4
GND
CLKC5
CLKT5
VDD
CLKT6
CLKC6
GND
CLKC7
CLKT7
VDD
PD#
FB_INT
FB_INC
VDD
FB_OUTC
FB_OUTT
GND
CLKC8
CLKT8
VDD
CLKT9
CLKC9
GND
ICS93V857
1
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5
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9
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46
45
44
43
42
41
40
39
38
37
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34
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28
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Functionality
PLL
FB_INT
FB_INC
CLK_INC
CLK_INT
PD#
Control
Logic
FB_OUTT
FB_OUTC
CLKT0
CLKT1
CLKT2
CLKT3
CLKT4
CLKT5
CLKT6
CLKT7
CLKT8
CLKT9
CLKC0
CLKC1
CLKC2
CLKC3
CLKC4
CLKC5
CLKC6
CLKC7
CLKC8
CLKC9
PRODUCT PREVIEW documents contain information on new
products in the sampling or preproduction phase of development.
Characteristic data and other specifications are subject to change
without notice.
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