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參數資料
| 型號： | ICS9248YG-50LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 6.10 MM, 0.65 MM PITCH, TSSOP-28 |
| 文件頁數： | 6/11頁 |
| 文件大小： | 261K |
| 代理商： | ICS9248YG-50LF-T |
4
ICS9248-50
PCI_STOP# Timing Diagram
PCI_STOP# is an asynchronous input to the ICS9248-50. It is used to turn off the PCICLK (0:4) clocks for low power
operation. PCI_STOP# is synchronized by the ICS9248-50 internally. The minimum that the PCICLK (0:4) clocks are enabled
(PCI_STOP# high pulse) is at least 10 PCICLK (0:4) clocks. PCICLK (0:4) clocks are stopped in a low state and started with
a full high pulse width guaranteed. PCICLK (0:4) clock on latency cycles are only one rising PCICLK clock off latency is one
PCICLK clock.
CPU_STOP# Timing Diagram
CPUSTOP# is an asychronous input to the clock synthesizer. It is used to turn off the CPUCLKs for low power operation.
CPU_STOP# is synchronized by the ICS9248-50. The minimum that the CPUCLK is enabled (CPU_STOP# high pulse) is 100
CPUCLKs. All other clocks will continue to run while the CPUCLKs are disabled. The CPUCLKs will always be stopped in a
low state and start in such a manner that guarantees the high pulse width is a full pulse. CPUCLK on latency is less than 4
CPUCLKs and CPUCLK off latency is less than 4 CPUCLKs.
Notes:
1. All timing is referenced to the internal CPUCLK.
2. CPU_STOP# is an asynchronous input and metastable conditions may exist.
This signal is synchronized to the CPUCLKs inside the ICS9248-50.
3. All other clocks continue to run undisturbed.
4. PD# and PCI_STOP# are shown in a high (true) state.
Notes:
1. All timing is referenced to the Internal CPUCLK (defined as inside the ICS9248 device.)
2. PCI_STOP# is an asynchronous input, and metastable conditions may exist. This signal is required to be synchronized
inside the ICS9248.
3. All other clocks continue to run undisturbed.
4. PD# and CPU_STOP# are shown in a high (true) state.
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相關代理商/技術參數 |
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|---|---|
| ICS9248YG-50T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS9248YG-50-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-56-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-92 | 制造商:ICS 制造商全稱:ICS 功能描述:Mobile Pentium IITM System Clock Chip |
| ICS9250-08 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
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