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參數(shù)資料
| 型號(hào)： | ICS9248YG-50LF-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 100 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 6.10 MM, 0.65 MM PITCH, TSSOP-28 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大?。?/td> | 261K |
| 代理商： | ICS9248YG-50LF-T |
2
ICS9248-50
Pin Descriptions
Pin number
Pin name
Type
Description
1
GNDREF
Power
Ground for 14.318 MHz reference clock outputs
2
X1
Input
14.318 MHz crystal input
3
X2
Output
14.318 MHz crystal output
4
PCICLK_F
Output
3.3 V free running PCI clock output, will not be stopped by the PCI_STOP#
5,6,9,10,11
PCICLK (1:5)
Output
3.3 V PCI clock outputs, generating timing requirements for Pentium II
7
GNDPCI
Power
Ground for PCI clock outputs
8
VDDPCI
Power
3.3 V power for the PCI clock outputs
12
VDD48
Power
3.3 V power for 48/24 MHz clocks
13
48 MHz
Output
3.3 V 48 MHz clock output, fixed frequency clock typically used with USB devices
14
TS#/48/24MHz
Output
3.3 V 48 or 24 MHz output and Tri-state option, active low = tri state mode for testing,
active high = normal operation
15
GND48
Power
Ground for 48/24 MHz clocks
16
SEL 100/66#
Input
control for the frequency of clocks at the CPU & PCICLK output pins. If logic "0" is
used the 66.6 MHz frequency is selected. If Logic "1" is used, the 100 MHz
frequency is selected. The PCI clock is multiplexed to run at 33.3 MHz for both
selected cases.
17
PD#
Input
Asynchronous active low input pin used to power down the device into a low power
state. The internal clocks are disabled and the VCO and the crystal are stopped. The
latency of the power down will not be greater than 3ms.
18
CPU_STOP#
Input
Asynchronous active low input pin used to stop the CPUCLK in active low state, all
other clocks will continue to run. The CPUCLK will have a "Turnon " latency of at
least 3 CPU clocks.
19
VDD
Power
Isolated 3.3 V power for core
20
PCI-Stop#
Input
Synchronous active low input used to stop the PCICLK in active low state. It will not
effect PCICLK_F or any other outputs.
21
GND
Power
Isolated ground for core
22
GNDL
Power
Ground for CPU clock outputs
23,24
CPUCLK(1:0)
Output
2.5 V CPU clock outputs
25
VDDL
Power
2.5 V power for CPU clock outputs
26
REF1/SPREAD#
Output
3.3 V 14.318 MHz reference clock output and power-on spread spectrum enable
option. Active low = spread spectrum clocking enable. Active high = spread spectrum
clocking disable.
27
REF0/SEL48#
Output
3.3 V 14.318 MHz reference clock output and power-on 48/24 MHz select option.
Active low = 48 MHz output at pin 14. Active high = 24 MHz output at pin 14.
28
VDDREF
Power
3.3 V power for 14.318 MHz reference clock outputs.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ICS9248YG-50T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Peripheral IC |
| ICS9248YG-50-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-56-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Timing Generator for Pentium II Systems |
| ICS9248YG-92 | 制造商:ICS 制造商全稱:ICS 功能描述:Mobile Pentium IITM System Clock Chip |
| ICS9250-08 | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for Celeron & PII/III⑩ |
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