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參數(shù)資料
| 型號： | ICS9248YG-192-T |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 66.6 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO28 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-28 |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 171K |
| 代理商： | ICS9248YG-192-T |
Integrated
Circuit
Systems, Inc.
ICS9248-192
0540F—10/27/05
SEL48_24#
CPU3.3V_2.5V#sel
SEL66/60#
PD#
PCI_STOP#
CPU_STOP#
SDATA
SCLK
PLL2
PLL1
Spread
Spectrum
48MHz
24_48MHz
CPUCLK0
PCICLK (5:0)
6
X1
X2
XTAL
OSC
CPU
DIVDER
PCI
DIVDER
Stop
Control
Logic
Config.
Reg.
/ 2
REF
Block Diagram
Frequency Timing Generator for Transmeta Systems
Pin Configuration
28-Pin TSSOP
Recommended Application:
Transmeta
Output Features:
1CPU(2.5V or 3.3V selectable) up to 66.6MHz &
overclocking of 66MHz.
6 PCI (3.3V) @ 33.3MHz (all are free running
selectable).
1 REF (3.3V) at 14.318MHz.
1 48MHz (3.3V).
1 24_48MHz selectable output.
Features:
Supports Spread Spectrum modulation for CPU and
PCI clocks, default -0.4 downspread.
Efficient Power management scheme through stop
clocks and power down modes.
Uses external 14.318MHz crystal, no external load
cap required for CL=18pF crystal.
28-pin TSSOP package, 4.40mm (173mil).
Skew Characteristics:
CPU – CPU <175ps
PCI – PCI < 500ps
CPU(early) – PCI = 1.5ns – 4ns.
GNDREF
X1
X2
PD#
PCICLK0
PCICLK1
PCICLK2
GNDPCI
VDDPCI
PCICLK3
PCICLK4
PCICLK5
SDATA
SCLK
VDDREF
REF
CPU_STOP#
VDDLCPU
GNDLCPU
CPUCLK0
PCI_STOP#
GND_Core
VDD_Core
SEL66/60#
VDD48
GND48
48MHz/CPU3.3v_2.5V#sel
24-48MHz/Sel48_24#
ICS9248-192
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Power Groups
VDD_Core, GND_Core = PLL core
VDDREF, GNDREF = REF, X1, X2
VDDPCI, GNDPCI = PCICLK (5:0)
VDD48, GND48 = 48MHz (1:0)
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