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參數(shù)資料
| 型號(hào)： | ICS9248YF-99 |
| 元件分類： | XO, clock |
| 英文描述： | 150.29 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 6/13頁 |
| 文件大?。?/td> | 255K |
| 代理商： | ICS9248YF-99 |
2
ICS9248-99
0314C—09/18/03
General Description
Pin Configuration
The ICS9248-99 is the single chip clock solution for Desktop
designs using 810/810/E style chipset. It provides all
necessary clock signals for such a system.
Spread spectrum may be enabled through I
2C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9248-
99
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2C interface allows changing functions,
stop clock programming and frequency selection.
Power Groups
GNDREF, VDDREF = REF1, X1, X2
GNDPCI , VDDPCI = PCICLK [7:0]
GNDSDR, VDDSDR = SDRAM [8:0]
GNDCOR, VDDCOR = supply for PLL core
GND3V66 , VDD3V66 = 3V66
VDD48 = 48MHz, 24_48MHz,
VDDLAPIC = IOAPIC
GNDLCPU , VDDLCPU = CPUCLK [1:0]
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
REF1
OUT
14.318 MHz reference clock.
FS3
IN
Frequency select pin.
2, 6, 16, 24, 27, 34,
42
VDD
PWR
3.3V Power supply for SDRAM output buffers, PCI output buffers,
reference output buffers and 48MHz output
3
X1
IN
Crystal input,nominally 14.318MHz.
4
X2
OUT
Crystal output, nominally 14.318MHz.
5, 9, 13, 20, 26, 30,
38
GND
PWR
Ground pin for 3V outputs.
8, 7
3V66 [1:0]
OUT
3.3V clock outputs
FS0
IN
Frequency select pin.
PCICLK0
OUT
PCI clock output.
FS1
IN
Frequency select pin.
PCICLK1
OUT
PCI clock output.
FS2
IN
Frequency select pin.
PCICLK2
OUT
PCI clock output.
19, 18, 17, 15, 14
PCICLK [7:3]
OUT
PCI clock outputs.
21, 22
48MHz
OUT
48MHz output clocks
SEL24_48#
IN
Select pin for enabling 24MHz or 48MHz
H=24MHz
L=48MHz
24_48MHz
OUT
Clock output for super I/O/USB
25
SDATA
IN
Data input for I2C serial input, 5V tolerant input
28
SCLK
IN
Clock input of I2C input, 5V tolerant input
29
PD#
IN
Asynchronous active low input pin used to power down the device into a low
power state. The internal clocks are disabled and the VCO and the crystal are
stopped. The latency of the power down will not be greater than 3ms.
31, 32, 33, 35, 36,
37, 39, 40, 41
SDRAM [8:0]
OUT
SDRAM clock outputs
43
GNDLCPU
PWR
Ground pin for the CPU clocks.
44, 45
CPUCLK [1:0]
OUT
CPU clock outputs.
46
VDDLCPU
PWR
Power pin for the CPUCLKs. 2.5V
47
IOAPIC
OUT
2.5V clock output.
48
VDDLAPIC
PWR
Power pin for the IOAPIC. 2.5V
23
1
11
12
10
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| ICS9248YG-101-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 |
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| ICS9248YG-162-T | 制造商:ICS 制造商全稱:ICS 功能描述:Frequency Generator & Integrated Buffers for PENTIUM/ProTM & K6 |
| ICS9248YG-171-T | 制造商:ICS 制造商全稱:ICS 功能描述:AMD - K7TM System Clock Chip |
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