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參數(shù)資料
| 型號： | ICS9248YF-99 |
| 元件分類： | XO, clock |
| 英文描述： | 150.29 MHz, PROC SPECIFIC CLOCK GENERATOR, PDSO48 |
| 封裝： | 0.300 INCH, SSOP-48 |
| 文件頁數(shù)： | 13/13頁 |
| 文件大小： | 255K |
| 代理商： | ICS9248YF-99 |
9
ICS9248-99
0314C—09/18/03
Absolute Maximum Ratings
Core Supply Voltage . . . . . . . . . . . . . . . . . . . . 4.6 V
I/O Supply Voltage . . . . . . . . . . . . . . . . . . . . . . 3.6V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . GND –0.5 V to VDD +0.5 V
Ambient Operating Temperature . . . . . . . . . . . 0°C to +70°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Stresses above those listed under
Absolute Maximum Ratings may cause permanent damage to the device.These ratings
are stress specifications only and functional operation of the device at these or any other conditions above those listed
in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = 0 - 70C; Supply Voltage VDD = 3.3V +5%, VDDL=2.5 V+-5%(unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Input High Voltage
VIH
2
VDD +
0.3
V
Input Low Voltage
VIL
VSS -
0.3
0.8
V
Input High Current
IIH
VIN = VDD = 0 V; Inputs with no
pull-up resistors
-5
5
mA
Input Low Current
IIL1
VIN = 0 V; Inputs with pull-up
resistors
-5
2
mA
Input Low Current
IIL2
VIN
-200
-100
mA
Operating Supply Current
IDD3.3OP
CL = 0 pF; Select @ 66M
60
100
mA
Power Down Supply Current
IDD3.3PD
CL = 0 pF; With input address to
Vdd or GND
400
600
A
Input frequency
Fi
14.32
MHz
Pin Inductance
Lpin
7nH
CIN
Logic Inputs
5
pF
Cout
Out put pin capacitance
6
pF
CINX
X1 & X2 pins
27
45
pF
Transition Time
1
Ttrans
To 1
st crossing of target Freq.
3ms
Settling Time
1
Ts
From 1
st crossing to 1% target
Freq.
3ms
Clk Stabilization
1
TSTAB
From VDD = 3.3 V to 1% target
Freq.
3ms
tPZH,tPZH
output enable delay (all outputs)
1
10
ns
tPLZ,tPZH
output disable delay(all outputs)
1
10
ns
1Guaranteed by design, not 100% tested in production.
Delay
Input Capacitance
1
VDD = 3.3 V;
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