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參數(shù)資料
| 型號(hào)： | ICS9219YGLF-T |
| 英文描述： | Direct Rambus Clock Generator Lite |
| 中文描述： | 直接Rambus的時(shí)鐘發(fā)生器建興 |
| 文件頁數(shù)： | 5/8頁 |
| 文件大小： | 80K |
| 代理商： | ICS9219YGLF-T |
5
ICS9219
0931B—10/25/04
Switching Characteristics over Recommended Operating Free-Air Temperature Range.
PARAMETER
MIN
TYP**
MAX
UNIT
t
(CYCLE)
1.8
3.7
ns
400 MHz
42
50
533 MHz
33
50
400 MHz
300
533 MHz
300
D
C
43%
51
53%
400 MHz
30
50
533 MHz
30
50
t
CR
, t
DF
Output rise and fall times (measured at
20%-80% of output voltage)
BUSCLKT/C
120
250
400
ps
t
RF
50
100
ps
t
CYCLE(L)
t
(CJ)
t
(CJ10)
D
C(2)
80
142.2
ns
-0.2
0.1
0.2
ns
-1.3 t
(CJ)
47%
1.3 t
(CJ)
53%
ns
Output duty cycle
REF
50
t
CRL
, t
CFL
Output rise and fall times (measured at
20%-80% of output voltage)
REF
0.8
1
ns
-3
-20
TEST CONDITIONS*
Clock cycle time (BUSCLKT/C)
See Figure 7
See Figure 7
Difference between rise and fall times on a single
device (20% ± 80%) |tCR - tCF|
Output duty cycle over 10,000 cycles
REF cycle jitter
REF 10-cycle jitter
Clock cycle time (REF)
See Figure 8
Measured at 50%
dB
PLL loop bandwidth
See Figure 7
fmod = 50 kHz
fmod = 8 MHz
ps
ps
ps
See Figure 6
See Figure 4
See Figure 3
See Figure 5
Total jitter over 1, 2, 3, 4, 5 or 6 clock
cycles
t
J
t
JL
t
DC,ERR
Output cycle-to-cycle duty cycle error
Long-term jitter
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